Patents by Inventor Mark Armstrong

Mark Armstrong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7312485
    Abstract: Complementary metal oxide semiconductor transistors are formed on a silicon substrate. The substrate has a {100} crystallographic orientation. The transistors are formed on the substrate so that current flows in the channels of the transistors are parallel to the <100> direction. Additionally, longitudinal tensile stress is applied to the channels.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: December 25, 2007
    Assignee: Intel Corporation
    Inventors: Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Paul A. Packan, Kelin J. Kuhn, Scott Thompson
  • Publication number: 20070246066
    Abstract: This invention pertains to a method for cleaning an automatic process device. The device is an apparatus for thermally treating a photosensitive element to form a relief surface. One or more contactable surfaces in the device can become contaminated with residue or other materials deposited from the photosensitive element during thermal treating and/or foreign bodies from ambient environment. A cleaning element having an adhesive layer on a support removes or reduces the level of contaminants on the contactable surface. The method includes passing the cleaning element through the device so that the adhesive layer contacts the contactable surfaces and thereby transfers at least one of the contaminants to the adhesive layer.
    Type: Application
    Filed: April 21, 2006
    Publication date: October 25, 2007
    Inventors: Hao Chang, Mark Armstrong
  • Publication number: 20070157581
    Abstract: A waste storage device includes a container (21) in which a cassette (1) is mounted. Tubing (2) is pulled through the centre of the cassette (1) to store packages (35) separated by twists. The cassette (1) is rotated relative to the container (21) to provide the twists between packages (35) by virtue of a rotatable disk (100) and user grip portion (102). The package is gripped against rotation by a gripper diaphragm (120) and is guided towards a wall of the container by a guide diaphragm (122) to prevent untwisting between packages.
    Type: Application
    Filed: October 21, 2004
    Publication date: July 12, 2007
    Applicant: SANGENIC INTERNATIONAL LIMITED
    Inventors: Ian Webb, Mark Armstrong
  • Patent number: 7226824
    Abstract: Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Armstrong, Harold Kennel, Tahir Ghani, Paul A. Packan, Scott Thompson
  • Publication number: 20070119963
    Abstract: A clip on type air freshener device having a housing with openings in walls thereof permitting air flow through a cavity in the housing. A bottle that holds a supply of fragrance bearing liquid is mounted on the housing and has a wick with a portion thereof projecting into the cavity in the housing. An open ended sleeve is mounted on housing in axial alignment with such projecting wick portion and is adjustably moveable axially along the wick selectively in one position to completely cover the wick projecting portion and in another position leave at least a major portion thereof exposed to air flow through said housing openings. The wick cover is exposed through an opening in the housing giving the user a visual indication as to the amount of wick exposed for evaporation of the fragrance during usage of the device.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 31, 2007
    Inventors: Anna DiBello, Mark Armstrong, Henri Spaile, David Petrarcic, Ed Kopinski
  • Patent number: 7187057
    Abstract: Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: March 6, 2007
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Armstrong, Harold Kennel, Tahir Ghani, Paul A. Packan, Scott Thompson
  • Publication number: 20070034945
    Abstract: Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.
    Type: Application
    Filed: October 24, 2006
    Publication date: February 15, 2007
    Inventors: Mark Bohr, Tahir Ghani, Stephen Cea, Kaizad Mistry, Christopher Auth, Mark Armstrong, Keith Zawadzki
  • Publication number: 20060286807
    Abstract: Embodiments relate to a substrate or wafer edge support having an emmisivity greater than that of a silicon wafer, where the edge support is for supporting a wafer during processing to form circuit devices on or in the wafer. Embodiments also include temperature sensors, heat conducting gas jets, and photonic energy can be directed to sense and control the temperature of the edge support and/or wafer edge during annealing to reduce temperature roll-off or roll-up at the edge as compared to the center of the wafer. Specifically, use of an edge support having an emmisivity greater than or equal to that of the wafer during processing allows helium gas jets directed at the edge support and/or wafer edge to reduce temperature roll-up at the edge during annealing. Because wafers from different processes and anneal locations may all have different emmisivities, use of the feedback loop will enable one edge ring to support the uniform anneal of wafers with a range of different emmisivities.
    Type: Application
    Filed: June 16, 2005
    Publication date: December 21, 2006
    Inventors: Jack Hwang, Robert James, Eric Lambert, Jonathan Leonard, Richard Brindos, Karson Knutson, Mark Armstrong, Justin Sandford
  • Patent number: 7129533
    Abstract: A method and apparatus to form a high-concentration, indium-fluorine retrograde well within a substrate. The indium-fluorine retrograde well includes an indium concentration greater than about 3E18/cm3.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark A. Armstrong, Stephen M. Cea, Giuseppe Curello, Sing-Chung Hu, Aaron D. Lilak, Max Wei
  • Publication number: 20060208337
    Abstract: A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.
    Type: Application
    Filed: May 24, 2006
    Publication date: September 21, 2006
    Inventors: Giuseppe Curello, Thomas Hoffmann, Mark Armstrong
  • Patent number: 7103003
    Abstract: A communications packet network is planned by the use of a planning tool. The tool comprises an input for inputting requirements of the network; and an input for determining factors which effect the passage of packet based data through the network. A modelling module determines the performance of the network based on the requirements and factors. The performance of model is compared with that of an objective comparison model. A feedback mechanism iteratively adjusts the input factors to improve the performance and maintain the network requirements. When the desired performance level is achieved, a plan of the network is output from the planning tool.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: September 5, 2006
    Assignee: Nortel Networks Limited
    Inventors: Simon Brueckheimer, Francois Blouin, Roger Britt, Mark Armstrong
  • Patent number: 7101765
    Abstract: A semiconductor device having high tensile stress. The semiconductor device comprises a substrate having a source region and a drain region. Each of the source region and the drain region includes a plurality of separated source sections and drain sections, respectively. A shallow trench isolation (STI) region is formed between two separated source sections of the source region and between two separated drain sections of the drain region. A gate stack is formed on the substrate. A tensile inducing layer is formed over the substrate. The tensile inducing layer covers the STI regions, the source region, the drain region, and the gate stack. The tensile inducing layer is an insulation capable of causing tensile stress in the substrate.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Thomas Hoffmann, Mark Armstrong
  • Publication number: 20060154536
    Abstract: A marine propulsion system comprising a push rod (50) for adjusting the pitch of propeller blades (34). The push rod (50) has a screw-threaded bolt (60) engaged with a nut (78). The nut (78) carries a bevel gear (84) by which the nut (78) can be rotated to cause the bolt (60) and therefore the push rod (50) to move longitudinally. The push rod (50) is connected to a claw with arms couple with pins (170). The pins (170) engage eccentric shafts (174) for unlocking a propeller base (190) so the base (190) can rotate around a transverse axis. The base (190) has an inclined surface which engages with an inclined surface defining an opening in the propeller's hub therefore locking the propeller blade (34) in position. The inclined surfaces are disengaged by rotation of the eccentric shaft (174) thus the propeller blades (34) can be rotated to adjust the pitch and than the inclined surfaces re-engage locking the propeller blade (34) in the pitch adjusted position.
    Type: Application
    Filed: July 20, 2004
    Publication date: July 13, 2006
    Applicant: Aimbridge Pty Ltd
    Inventors: Hans-Gunther Rosenkranz, Dmitri Shmatkov, Mark Armstrong
  • Patent number: D521249
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: May 23, 2006
    Assignee: Hayco Manufacturing Limited
    Inventors: Christopher James McCaughan Hay, Mark Armstrong
  • Patent number: D527189
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: August 29, 2006
    Assignee: Hayco Manufacturing Limited
    Inventors: Christopher James Mccaughan Hay, Mark Armstrong
  • Patent number: D533785
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: December 19, 2006
    Assignee: Cadbury Schweppes Plc
    Inventors: John Corbett, Denise Lefebvre, Grant Thomas Briggs, Lori Evans Bartman, Edouard Didier John Irvine Ball, Ian Webb, Mark Armstrong, Edward Adamson
  • Patent number: D536255
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: February 6, 2007
    Assignee: Cadbury Schweppes Plc
    Inventors: John Corbett, Denise Lefebvre, Grant Thomas Briggs, Lori Evans Bartman, Edouard Didier John Irvine Ball, Ian Webb, Mark Armstrong, Edward Adamson
  • Patent number: D537981
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: March 6, 2007
    Assignee: The Procter & Gamble Company
    Inventor: Mark Armstrong
  • Patent number: D545210
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: June 26, 2007
    Assignee: Unilever Bestfoods North America division of Conopco, Inc.
    Inventors: Mark Armstrong, Timothy Frederik Perry, Ian Alexander Webb
  • Patent number: D545211
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: June 26, 2007
    Assignee: Conopco, Inc.
    Inventors: Mark Armstrong, Timothy Frederik Perry, Ian Alexander Webb