Patents by Inventor Mark B. Rosenbluth
Mark B. Rosenbluth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11258887Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.Type: GrantFiled: June 23, 2020Date of Patent: February 22, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ilan Pardo, Mark B. Rosenbluth, Idan Burstein, Rui Xu, Oded Lempel, Tsofia Eshel
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Publication number: 20210397560Abstract: In one embodiment, a computer server system includes a memory to store data across memory locations, multiple processing cores including respective local caches in which to cache cache-lines read from the memory, an interconnect to manage read and write operations of the memory and local caches, maintain local cache location data of the cached cache-lines according to respective ones of the memory locations from which the cached cache-lines were read from the memory, receive a write request for a data element to be written to one of the memory locations, find a local cache location in which to write the data element responsively to the local cache location data and the memory location of the write request, and send an update request to a first processing core to update a respective first local cache with the data element responsively to the found local cache location.Type: ApplicationFiled: June 22, 2020Publication date: December 23, 2021Inventors: Ilan Pardo, Hillel Chapman, Mark B. Rosenbluth
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Publication number: 20210400124Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.Type: ApplicationFiled: June 23, 2020Publication date: December 23, 2021Inventors: Ilan Pardo, Mark B. Rosenbluth, Idan Burstein, Rui Xu, Oded Lempel, Tsofia Eshel
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Patent number: 11016895Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.Type: GrantFiled: April 6, 2018Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Frank T. Hady, Mason Cabot, Mark B. Rosenbluth, John Beck
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Patent number: 10942876Abstract: One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers ofType: GrantFiled: November 14, 2019Date of Patent: March 9, 2021Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Carl Ramey, Christopher Jackson, Diane Orf, Matt Orsini, Michael Cotsford, Mark B. Rosenbluth, Rui Xu
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Patent number: 10877761Abstract: A multiprocessor device includes cores and at least one ingress-write ordering circuitry (IWOC) including first and second counters associated with first and second destinations. The IWOC is configured to assign sequential numbers to write transactions received from a source, according to an order of reception at the IWOC, and to forward the write transactions from the IWOC to the first and second write-transaction destinations, while preserving the order, by incrementing the first and second counters such that both the first counter and the second counter track a sequential number of a next write transaction that the IWOC will forward, forwarding a first write transaction to the first destination only provided that the sequential number of the first write transaction matches the first counter, and forwarding a second write transaction to the second destination only provided that the sequential number of the second write transaction matches the second counter.Type: GrantFiled: December 8, 2019Date of Patent: December 29, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Rui Xu, Carl Ramey, Benjamin Cahill, Diane Orf, Mark B. Rosenbluth, Michael Cotsford
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Patent number: 10339061Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.Type: GrantFiled: December 15, 2016Date of Patent: July 2, 2019Assignee: Intel CorporationInventors: Frank T. Hady, Mason Cabot, Mark B. Rosenbluth, John Beck
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Publication number: 20190114261Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.Type: ApplicationFiled: April 6, 2018Publication date: April 18, 2019Inventors: FRANK T. HADY, MASON CABOT, MARK B. ROSENBLUTH, JOHN BECK
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Patent number: 9965393Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.Type: GrantFiled: December 22, 2015Date of Patent: May 8, 2018Assignee: Intel CorporationInventors: Frank T. Hady, Mason Cabot, Mark B. Rosenbluth, John Beck
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Publication number: 20170097889Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Inventors: FRANK T. HADY, MASON CABOT, MARK B. ROSENBLUTH, JOHN BECK
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Publication number: 20170097888Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Inventors: FRANK T. HADY, MASON CABOT, MARK B. ROSENBLUTH, JOHN BECK
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Patent number: 9535838Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: November 30, 2012Date of Patent: January 3, 2017Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Patent number: 9442855Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: December 27, 2014Date of Patent: September 13, 2016Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20160188466Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.Type: ApplicationFiled: December 22, 2015Publication date: June 30, 2016Inventors: Frank T. Hady, Mason Cabot, Mark B. Rosenbluth, John Beck
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Patent number: 9235550Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.Type: GrantFiled: June 30, 2014Date of Patent: January 12, 2016Assignee: Intel CorporationInventors: Frank T. Hady, Mason B. Cabot, John Beck, Mark B. Rosenbluth
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Patent number: 9098415Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: November 30, 2012Date of Patent: August 4, 2015Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20150161050Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: December 27, 2014Publication date: June 11, 2015Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Publication number: 20150149683Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: ApplicationFiled: November 30, 2012Publication date: May 28, 2015Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Patent number: 9032103Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: December 6, 2012Date of Patent: May 12, 2015Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
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Patent number: 9026682Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.Type: GrantFiled: December 13, 2012Date of Patent: May 5, 2015Assignee: Intel CorporationInventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia