Abstract: Methods and apparatus, including computer program products, for a write queue descriptor count instruction for high speed queuing. A write queue descriptor count command causes a processor to write a single word containing a queue count for each of a plurality of queue entries in a queue array cache.

Abstract: In general, in one aspect, the disclosure describes storing identification of one or more memory buckets associated with different, respective, queued write commands, and, based on the stored identification, determining whether at least one bucket associated with a read command is included in one or more buckets associated with at least one queued write command.

Abstract: Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.

Abstract: A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.

Abstract: A lookup mechanism provides an input value to a datapath element disposed in an execution datapath of a processor and causes the datapath element to compare the input value to stored identifier values. The lookup mechanism receives from the datapath element a result based on the comparison.

Abstract: A device and method for processing a data packet at a device are described. The device receives data packets and determines available memory in one or more of local memories of a plurality of execution threads. The device stores packet information in an available one of the local memories of the execution threads.

Abstract: A system and a method for creating a serial chain of processors on a line card to allow longer processing time on a data set is disclosed. Each processor in the chain partially processes the data set, converts the data set to an interface protocol, and then transmits the data set to the next processor in the chain. A bus interconnects each processor in the chain with the processor immediately precedent, allowing flow control information to be sent back. A loop back configuration can allow for additional processing of data within a switching fabric before transmission to a network.

Abstract: The use of enqueue operations to append multi-buffer packets to the end of a queue includes receiving a request to place a string of linked buffers in a queue, specifying a first buffer in the string and a queue descriptor associated with the first buffer in the string, updating the buffer descriptor that points to the last buffer in the queue to point to the first buffer in the string, and updating a tail pointer to point to the last buffer in the string.

Abstract: Memory interleaving includes providing a non-power of two number of channels in a computing system and interleaving memory access among the channels.

Abstract: A method of ordering commands includes receiving a set of related commands that have a predetermined execution sequence, the commands being received in an arbitrary order that may be different from the execution sequence and releasing a later received command of the set for execution before an earlier received command from the set based on the execution sequence.

Abstract: In general, in one aspect, the disclosure describes storing identification of one or more memory buckets associated with different, respective, queued write commands, and, based on the stored identification, determining whether at least one bucket associated with a read command is included in one or more buckets associated with at least one queued write command.

Abstract: A method of managing a free list and ring data structure, which may be used to store journaling information, by storing and modifying information describing a structure of the free list or ring data structure in a cache memory that may also be used to store information describing a structure of a queue of buffers.

Abstract: A system and method for reassembling c-frames into coherent packets are disclosed. C-frames contain segments of a data set. A micro-engine operating multiple threads copies the data set segments into assigned queues, following a thread hierarchy to keep the segments in order. The queues are stored in SRAM. The micro-engine maintains a subset of the total number of queues in local memory. If a segment belongs to a queue not in local memory, the least recently used queue is copied to SRAM, the required queue is read from SRAM, and the queue is updated with the data set segment.

Abstract: Processor architectures, and in particular, processor architectures that assemble data segments into full packets for efficient packet-based classification. In accordance with an embodiment of the present invention, a method for assembling received data segments into full packets in an initial processing stage in a processor includes receiving a plurality of data segments from a packet, determining a first storage location for each of the plurality of data segments, and storing each of the plurality of data segments in its determined first storage location. The method also includes determining a second storage location for each of the plurality of data segments, said second storage locations being logically ordered to represent the order the data segments originally occurred in the packet and storing each of the plurality of data segments in its determined second storage location to re-assemble the packet.

Abstract: Embodiments described herein provide a system and method that advantageously reduces the number of internal signals required to monitor the performance of a network processor. A plurality of events may be selected from a predetermined number of design unit events, and a plurality of signals may be selected from a predetermined number of design unit signals. A plurality of counters may be associated with the plurality of signals, and for each of the plurality of signals, a number of event occurrences may be counted and sent to a processor unit.

Abstract: In-band flow control data may be received from a switch fabric at a first network processor. The received in-band flow control data may be transmitted to a second network processor using a flow control bus. The second network processor may determine which receive queues in the switch fabric exceed a predetermined overflow threshold based on the in-band flow control data. The second processor may transmit data to the receive queues in the switch fabric determined not to exceed the predetermined overflow threshold.

Abstract: The invention features a method for transferring data to programming engines using multiple memory channels, parsing data over at most two channels in the memory channels, and establishing at most two logical states to signal completion of a memory transfer operation.

Abstract: A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.

Abstract: A method and apparatus for processing data packets including generating an enqueue command specifying a queue descriptor associated with a new buffer. The queue descriptor is part of a cache of queue descriptors each having a head pointer pointing to a first buffer in a queue of buffers, and a tail pointer pointing to a last buffer in the queue. The first buffer having a buffer pointer pointing to next buffer in the queue. The buffer pointer associated with the last buffer and the tail pointer is set to point to the new buffer.

Abstract: A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between programming stages, which correspond to the programming engines. The method also includes establishing contexts for the assigned tasks on the programming engines and using a software controlled cache such as a CAM to transfer data between next neighbor registers residing in the programming engines.