Abstract: A dynamic random access memory (DRAM) cell is formed with a buried strap which is routed through an isolation trench. This structure frees space in the transfer gate such that the location of the buried strap is not a limiting factor for decreasing the size of DRAM cells.

Abstract: Five square dynamic random access memory (DRAM) cell is prepared with a vertical transfer device with long channel length. In this construction, channel length is not affected by cell size scaling requirements.

Abstract: A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.

Abstract: A high capacitance storage node structure is created in a substrate by patterning a hybrid resist (12) to produce both negative tone (16) and positive tone (18) areas in the exposed region (14). After removal of the positive tone areas (18), the substrate (12) is etched using the unexposed hybrid resist (12) and negative tone area (16) as a mask. This produces a trench (22) in the substrate (12) with a centrally located, upwardly projecting protrusion (24). The capacitor (26) is then created by coating the sidewalls of the trench (22) and protrusion (24) with dielectric (28) and filling the trench with conductive material (30) such as polysilicon.

Abstract: A transfer metal configuration and fabrication process possessing increased probability of intersecting a transverse metallization level are presented, without employing an increase in actual metal thickness. The transfer metal is configured with a non-rectangular transverse cross-section such that the thickness of the electrical connect remains the same, but the transverse contact area of the exposed metal is increased. The entire transfer metal may have the same transverse cross-sectional configuration or have portions with different transverse configurations. If different configurations are employed, each portion of the transfer metal to be transversely intersected has the enhanced cross-sectional configuration. A tiered transverse configuration is presented which facilitates electrical connection of the transfer metal to a metal level on a face of a semiconductor cube structure.

Abstract: Disclosed is a process for forming a film comprising a polysilane composition on a substrate. The film is formed by vapor deposition directly on a substrate, thus avoiding the cumbersome steps ordinarily encountered in preparing and applying polysilanes by conventional spin application techniques. The film is used in a lithographic process for forming an image on a substrate.

Abstract: An optical photolithographic process in which resist lines having widths in the micron and sub-micron range are produced without the use of a fine line photomask. A positive photoresist having an additive for image reversal is applied to the surface of a semiconductor substrate. The photoresist is exposed through a photomask to ultraviolet light. The edges of the opaque sections of the mask diffract the ultraviolet light, forming partially exposed areas between the exposed and unexposed areas formed in the photoresist. After development in a solvent to remove the exposed areas, the photoresist undergoes an image reversal process. The photoresist is first baked at 100.degree. C. for 30 minutes. During this bake step, the photoactive decomposition products present in the partially exposed areas react, freezing the solubility of the partially exposed areas with respect to that of the unexposed areas.

Abstract: The present invention describes conformable masking techniques which can be successfully made and used in a practical manufacturing environment while providing increased resolution of photolithographic images while eliminating all manner of defects that might presently be encountered in the masks currently used in the semiconductor industry.In the present invention a body is first coated with a positive photoresist overcoated with a conformable mask which is exposed through a fixed mask and developed to define a replica of the fixed mask, together with all its defects. The underlying photoresist is then exposed to light through developed openings in the conformable mask. The conformable mask is then stripped and a new conformable mask laid down. This new conformable mask is now exposed through a second fixed mask having the same image as the first fixed mask, but presumably with different defects and developed to define a replica of the second mask.