Abstract: Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.

Abstract: A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

Abstract: Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.

Abstract: A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system.

Abstract: The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.

Abstract: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

Abstract: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.

Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

Abstract: A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing.

Abstract: A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing.

Abstract: A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

Abstract: A carbon nanotube filter. The filter including a filter housing; and chemically active carbon nanotubes within the filter housing, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and media containing the chemically active carbon nanotubes.

Abstract: An exposure system for exposing a photoresist layer on a top surface of a wafer to light. The exposure system including: an environment chamber containing a light source, one or more focusing lenses, a mask holder, a slit and a wafer stage, the light source, all aligned to an optical axis, the wafer stage moveable in two different orthogonal directions orthogonal to the optical axis, the mask holder and the slit moveable in one of the two orthogonal directions; a filter in a sidewall of the environment chamber, the filter including: a filter housing containing chemically active carbon nanotubes, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and means for forcing air or inert gas first through the filter then into the environment chamber and then out of the environment chamber.

Abstract: A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing.

Abstract: An air particle precipitator and a method of air filtration comprise a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further comprises an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further comprise a metal layer over the carbon nanotube.

Abstract: A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the polymer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

Abstract: Methods of forming a gas dielectric and a related structure are disclosed. In one embodiment, the method includes providing a wiring level including at least one conductive portion within a sacrificial dielectric; forming a nanofiber layer over the wiring level; vaporizing the sacrificial dielectric by heating; evacuating the vaporized sacrificial layer; and sealing pores in the nanofiber layer.

Abstract: The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the doped substrate region has a first polarity opposite a second polarity of the channel region. The isolation region contacts the doped substrate region. The structure further includes a gate electrode covering the channel region and at least a portion of the isolation region. The gate electrode comprises a lower portion below the channel region of the fin, wherein the lower portion of the gate electrode comprises a height that is at least one-half of a thickness of the fin.

Abstract: Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

Abstract: An air particle precipitator and a method of air filtration include a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further includes an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further include a metal layer over the carbon nanotube.