Abstract: A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first multiplexer, and the DDR clock and reference clock are inputs to a second multiplexer. In normal operation the multiplexers provide the CPU and DDR clock signal as outputs. To reprogram the clock frequencies and reset the PLL, (1) the reference clock signal is selected to be the output of both multiplexers, so the device is running on the internal reference clock. The mux switching is synchronized with the CPU and DDR clock signals. (2) The PLL is reprogrammed, its internal voltage-controlled oscillator is reset, and the PLL is restarted at the new desired frequency. (3) When the new PLL frequency output is stable, the multiplexers are switched back to the PLL-generated CPU and DDR clocks, synchronously with the reference clock signal.

Abstract: An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal.

Abstract: A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal.

Abstract: A disk drive controller includes a servo system operable to associate a time stamp with an arrival of a servo wedge, a firmware loop and core PLLs in the read channel. The firmware loop is operable to determine a period between the arrival of a pair of consecutive servo wedges and produce a desired frequency of when to read/write data to disk based on the period between the arrival of a pair of consecutive servo wedges. Processing circuitry is operable to adjust a clock signal, wherein the clock signal itself is not locked to the data and produce a fine control signal for the core PLLs in the read channel. These core PLLs are operable to determine a phase and/or frequency associated with when an analog signal is sampled and/or written to disk, wherein these core PLLs comprises Fractional N Sigma Delta PLLs.

Abstract: A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: Novel [1.2.4]triazolo[1,5-a]pyrazine compounds are disclosed that have a formula represented by the following: The compounds may be prepared as pharmaceutical compositions, and may be used for the prevention and treatment of a variety of conditions in mammals including humans, including by way of non-limiting example, pain, inflammation, and others.

Abstract: The present invention relates to frequency dividers. The frequency divider comprises an input, a counter, a first comparator, an interconnect, and an output. The counter has a counter reset port and is configured to receive a clock signal from the input and to produce a sum signal. The first comparator is configured to receive the sum signal, to compare the sum signal to a first integer, and to produce a first comparison signal. The interconnect is configured to convey the first comparison signal from the first comparator to the counter reset port. The output coupled to the first comparator. The clock signal has a periodic waveform. The sum signal represents a first sum, which equals a number of waveforms of the clock signal received by the counter after the counter has been reset. In a first embodiment, the first integer is selectable from a set of at least three consecutive integers. In a second embodiment, a frequency of the clock signal is at least 1.5 gigahertz.

Abstract: Methods of processing incoming documents. The methods may comprise receiving a plurality of documents in electronic form and classifying each of the plurality of documents into at least one of a plurality of document classifications. The methods may also comprise extracting metadata from the plurality of documents. In addition, the methods may comprise executing a first workflow for processing documents classified in a first document classification selected from the plurality of document classifications and executing a second workflow for processing documents classified in a second document classification selected from the plurality of document classifications.

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: Novel imidazo[1,2-a]pyrazine compounds are disclosed that have a formula represented by the following: The compounds may be prepared as pharmaceutical compositions, and may be used for the prevention and treatment of a variety of conditions in mammals including humans, including by way of non-limiting example, arthritis, inflammation, and others.

Abstract: Compounds of formula (I) are potent and selective 5-HT2A antagonists, useful in treatment of a variety of adverse conditions of the CNS.

Abstract: At least one method for indicating a weather condition includes indexing a storm based on two or more parameters. One of the parameters is a travel speed of the storm and a second parameter is a location of the storm. The method further includes providing a time before the storm impacts a recipient based on the travel speed of the storm and a track distance to the recipient location. The method further includes delivering the time before the storm impacts the location to the recipient.

Abstract: At least one method for characterizing cyclone includes combining a first parameter with at least a second parameter.

Abstract: At least one method for indicating a weather condition. The method includes providing a probability of one or more wind fields from a cyclone impacting one or more locations over a period of time. The probability may then be delivered to a recipient.

Abstract: An embodiment of the invention provides an apparatus and method for varying a voltage controlled oscillator (VCO) sensitivity. A VCO has an oscillator portion coupled to a variable current supply. The variable current supply has one or more enabled variable current cells. The enable variable current cell input provides a control to change the VCO sensitivity. In an example, the oscillator portion has a ring oscillator. In an example, the variable current supply has at least two variable current cells that supply the control current. A binary control signal alters a quantity of variable current cells that supply the control current. Each successive variable current cell has an output current substantially equal to twice that of a prior variable current cell.

Abstract: The present invention provides a method of treatment of a subject suffering from a disease, such as schizophrenia, for which the administration of an NK-3 antagonist is indicated which comprises administering to that subject a therapeutically effective amount of a compound of formula I: wherein, generally, Q is R1 is benzyl, phenyl, thiophene or imidazolyl optionally substituted with C1-4alkyl or halogen, such as methyl, fluorine or bromine; R2 is hydrogen or C1-4alkyl such as methyl; R3 is phenyl; R4 is hydrogen; R5 is hydrogen or C1-6alkylcarbonyl such as methylcarbonyl; X is —SO2— or —C(O)N(R2)SO2— where R2 is preferably hydrogen; Y is a bond, CH2 or Z1 where Z1 is —N(Rf)— in which Rf is C1-6alkylcarbonyl such as ethylcarbonyl; and R6 is phenyl, pyrazolyl, pyridyl, pyrimidinyl or benzimidazolonyl optionally substituted with one or two groups chosen from C1-6alkyl and benzyl, such as methyl, ethyl and benzyl; or a pharmaceutically acceptable salt thereof.

Abstract: Provided herein is a process for generating steam comprising supplying a first stream to a steam reformer to produce a second stream comprising essentially 100% steam such that the molecular composition of the first stream is identical to the molecular composition of second stream, wherein the steam reformer comprises a reformer inlet in fluid communication with a reformer outlet, and at least one tube arranged between, and in fluid communication with the reformer inlet and the reformer outlet; and wherein the at least one tube is in thermal communication with a furnace of the steam reformer. A steam reformer for producing steam is also disclosed.

Abstract: The present invention relates to frequency dividers. The frequency divider comprises an input, a counter, a first comparator, an interconnect, and an output. The counter has a counter reset port and is configured to receive a clock signal from the input and to produce a sum signal. The first comparator is configured to receive the sum signal, to compare the sum signal to a first integer, and to produce a first comparison signal. The interconnect is configured to convey the first comparison signal from the first comparator to the counter reset port. The output coupled to the first comparator. The clock signal has a periodic waveform. The sum signal represents a first sum, which equals a number of waveforms of the clock signal received by the counter after the counter has been reset. In a first embodiment, the first integer is selectable from a set of at least three consecutive integers. In a second embodiment, a frequency of the clock signal is at least 1.5 gigahertz.