Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: The compounds of formula (I): inhibit gamma-secretase and hence are of utility in the treatment or prevention of Alzheimer's disease.

Abstract: The present invention discloses a compound of formula (I): wherein: R1 is an aryl or heteroaryl ring; R2 is hydroxy, C1-6 alkoxy, C1-6 alkyl, amino, NR?R? or C1-6 alkyl-NR?R? where R? and R? are independently chosen from hydrogen and C1-4 alkyl and where R? and R?, together with the nitrogen atom to which they are attached, form a saturated nitrogen-containing 3-7 membered heterocycle optionally containing a further nitrogen atom and optionally substituted by NR?R? as defined above or R2 is C1-6 alkoxy substituted by NR?R? as defined above; R3 is hydrogen or C1-6 alkyl; R4 is hydrogen, C1-8 alkyl, C2-8 alkenyl, C2-8 alkynyl, C3-8 cycloalkyl, aryl or aryl C1-6 alkyl; R5 is hydrogen, C1-8 alkyl, C2-8 alkenyl, C2-8 alkynyl, C3-8 cycloalkyl, aryl, aryl C1-6 alkyl or C1-6 alkoxycarbonyl; or R4 and R5, together with the nitrogen atom to which they are attached, form a C3-C10 mono- or bicyclic saturated ring; X and Y are independently chosen from hydrogen, hydroxy, nitro, amino, cyano, CF3, halogen and C1-4 alkyl; o

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A class of imidazo[1,2b][1,2,4]triazine derivatives, substituted at the 7-position by an optionally substituted five-membered or six-membered heteroaromatic ring, being selective ligands for GABAA receptors, in particular having good affinity for the ?2 and/or ?3 and/or ?5 subunit thereof, are accordingly of benefit in the treatment and/or prevention of adverse conditions of the central nervous system, including anxiety, convulsions and cognitive disorders.

Abstract: The present invention provides a pharmaceutical composition providing a compound of formula I or a pharmaceutically acceptable salt thereof in a pharmaceutically acceptable excipient: (I), in which: X and Y independently represent CH or N, with the proviso that if X is CH then Y is also CH; R1 represents hydrogen, hydrocarbon, a heterocyclic group, halogen, cyano, trifluoromethyl, nitro, —ORa, —SRa, —SORa, —SO2Ra, —SO2NRaRb, —NRaRb, —NRaCORb, —NRaCO2Rb, —CORa, —CO2Ra, —CONRaRb or CRa?NORb; Ra and Rb independently represent hydrogen, hydrocarbon or a heterocyclic group; V and W are independently selected from H, halogen, C11-6alkyl, OH and C-1-6alkoxy; Z represents H, halogen, CN, NO2, CF3, OCF3, CF2H, SCF3, R2, OR3, SR3, (CH2)pN(R3)2, O(CH2)pN(R3)2, SO2R2, SO2N(R3)2, COR4, CO2R3, CON(R3)2, NHCOR4, NR1(CH2)nheteroaryl or O(CH2)nheteroaryl the heteroaryl is optionally substituted by one, two or three groups chosen from C1-6alkyl, benzyl, (CH2)pN(R3)2, halogen and CF3, R1 is C1-6alkyl, where n is 1 or 2 and p is

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first multiplexer, and the DDR clock and reference clock are inputs to a second multiplexer. In normal operation the multiplexers provide the CPU and DDR clock signal as outputs. To reprogram the clock frequencies and reset the PLL, (1) the reference clock signal is selected to be the output of both multiplexers, so the device is running on the internal reference clock. The mux switching is synchronized with the CPU and DDR clock signals. (2) The PLL is reprogrammed, its internal voltage-controlled oscillator is reset, and the PLL is restarted at the new desired frequency. (3) When the new PLL frequency output is stable, the multiplexers are switched back to the PLL-generated CPU and DDR clocks, synchronously with the reference clock signal.

Abstract: A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.

Abstract: A class of 7-phenylimidazo[1,2-b][1,2,4]triazine derivatives, substituted at the meta position of the phenyl ring by an optionally substituted aryl or heteroaryl group which is directly attached or bridged by an oxygen atom or a —NH— linkage, and substituted on the phenyl ring by one or two further substituents as defined herein, being selective ligands for GABAA receptors, in particular having good affinity for the ?2 and/or ?3 and/or ?5 subunit thereof, are accordingly of benefit in the treatment and/or prevention of adverse conditions of the central nervous system, including anxiety, convulsions and cognitive disorders.

Abstract: Compositions and methods for enhancing the immunity of a subject or vaccinating a subject against mycobacterial infections are disclosed. The invention provides compositions comprising formalin inactivated cultures of a mycobacterium, such as M. bovis, and a Novasome® adjuvant, as well as methods for using such compositions.

Abstract: Compounds of formula I: are antagonists of the human 5-HT2A receptor, and hence useful in treatment or prevention of a variety of neurological conditions.

Abstract: A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Abstract: A signal driving system generates an output swinging between a first power supply (e.g., about 1.2 Volts), powering first and second drivers, and a second power supply (e.g., about 3.3 Volts), powering a first current mirror. The second power supply is generated external to the signal driving system and is used to allow for a desired common-mode differential output signal range. However, the second power supply produces voltage at a level above a rating of the devices in the signal driving system. Therefore, protection devices are used to protect the elements of the signal driving system from the second power supply. Accordingly, through use of the signal driving system of the present invention, a high voltage current mode driver can operate in a low voltage process without damaging the devices in the signal driving system.

Abstract: A system and method are used to accelerate settling or steady state of an amplifier in an amplifier system. This is used to ensure the amplifier reaches steady-state within a specified time period from stand-by or another state without using more current than is needed for steady-state. A comparator in a common-mode feedback system compares a desired amplifier output signal to one or more nodes of the amplifier. A result of the comparison is compared to a threshold value using a comparator in a settling acceleration system. If the result crosses the threshold, a controller turns on a driver in the settling acceleration system. The driver pulls on one or more nodes of the amplifier, which, along with a driver in the amplifier system pulling on the node, quickly brings the amplifier to settling or steady state.