Patents by Inventor Mark Chang
Mark Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180020028Abstract: Computer-implemented techniques include detecting, using a camera of a computing device having one or more processors, a digital watermark displayed by a display of a computing system. The digital watermark can be a visual indicator that is detectable by the camera of the computing device, and the computing system can further comprise a set of speakers and a set of cameras. The techniques can include determining, by the computing device, a unique identifier for the computing system based on the digital watermark. The techniques can also include automatically coordinating, by the computing device, an audio/video conference session between the computing device and the computing system using the unique identifier.Type: ApplicationFiled: July 18, 2016Publication date: January 18, 2018Applicant: Google Inc.Inventor: Mark Chang
-
Publication number: 20170286366Abstract: A system and method for creating, sending, receiving, or displaying messages with smart variable expressive text or graphics is described. The method includes providing a user interface for inputting content and specifying an appearance of the content, receiving the content and an appearance control input via the user interface, responsive to the appearance control input, creating a message including the content and formatting information, and sending the message including the content and the formatting information.Type: ApplicationFiled: May 16, 2016Publication date: October 5, 2017Inventors: Mark Chang, Matthew Austin, James Buyayo, Jason Cornwell, Debbie Kim, Richard Lo, Johnathon Schlemmer, Christopher Tompkins, Megan Torkildson, Joy Barlow, Anton Volkov
-
Publication number: 20160273121Abstract: An electroplating method according to an embodiment is a electroplating method of generating a metal film on a cathode surface by setting a negative potential to a cathode of an anode and the cathode provided in a reaction bath, including mixing and accommodating a plating solution containing at least plated metal ions, an electrolyte, and a surface active agent and a supercritical fluid in the reaction bath and applying a current in a concentration of the supercritical fluid and a cathode current density in which a polarization resistance obtained from a cathode polarization curve while the plated metal ions are reduced is larger than before the supercritical fluid is mixed.Type: ApplicationFiled: March 9, 2016Publication date: September 22, 2016Applicants: KABUSHIKI KAISHA TOSHIBA, TOKYO INSTITUTE OF TECHNOLOGYInventors: Kazuhito HIGUCHI, Yusaku Asano, Kyoko Honma, Kazuma Hiraguri, Yasunari Ukita, Masayuki Uchida, Toshiya Nakayama, Mayumi Machino, Masato Sone, Tso-Fu Mark Chang
-
Publication number: 20160274471Abstract: A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.Type: ApplicationFiled: March 16, 2015Publication date: September 22, 2016Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Sheng-Chi Chin, Ting-Hao Hsu, Mark Chang
-
Patent number: 9445048Abstract: Systems and methods are disclosed for gesture-initiated actions in videoconferences. In one implementation, a processing device receives one or more content streams as part of a communication session. The processing device identifies, within the one or more content streams, a request for feedback. The processing device processes, based on an identification of a request for feedback within the one of the plurality of content streams, the one or more content streams to identify a presence of one or more gestures within at least one of the one or more content streams. The processing device initiates, based on an identification of the presence of one or more gestures within at least one of the one or more content streams, an action with respect to the communication session.Type: GrantFiled: July 29, 2014Date of Patent: September 13, 2016Assignee: GOOGLE INC.Inventors: Mehul Nariyawala, Rahul Garg, Navneet Dalal, Thor Carpenter, Greg Burgess, Tim Psiaki, Mark Chang, Antonio Bernardo Monteiro Costa, Christian Plagemann, Chee Chew
-
Patent number: 8935110Abstract: A system for analyzing an interior energy system including: at least one detachable sensor arranged to monitor a portion of the interior energy system; and an apparatus including a processor configured to receive data of a first parameter of the interior energy system from the at least one detachable sensor and determine a second parameter of the interior energy which is inferred on the basis of the received data of the first parameter; and determine a characteristic of the interior energy system from the determined second parameter. The system may provide analysis of the interior energy system and recommend improvements.Type: GrantFiled: October 26, 2009Date of Patent: January 13, 2015Assignee: The Technology Partnership PLCInventors: Mark Chang-Ming Hsieh, David Russell Anderson
-
Patent number: 8474539Abstract: The present disclosure provides an improved design for a pull tube sleeved stress joint and associated pull tube for managing stresses on a catenary riser for a floating offshore structure. The pull tube sleeve stress joint includes at least one sleeve surrounding a length of the pull tube with an annular gap between the sleeve and pull tube and a link ring therebetween. For embodiments having a plurality of sleeves, a first sleeve can be spaced by an annular first gap from the pull tube and coupled thereto with a first ring between the pull tube and the first sleeve, and a second sleeve can be spaced by an annular second gap from the first sleeve and coupled thereto with a second ring between the first sleeve and the second sleeve. Both pull tube and sleeves can be made with regular pipe segments welded together with regular girth welds.Type: GrantFiled: August 25, 2009Date of Patent: July 2, 2013Assignee: Technip FranceInventors: Michael Y. H. Luo, Bob Lixin Zhang, Shih-Hsiao Mark Chang
-
Patent number: 8445372Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.Type: GrantFiled: December 22, 2009Date of Patent: May 21, 2013Assignee: Spansion LLCInventors: Kyunghoon Min, Angela Hui, Hiroyuki Kinoshita, Ning Cheng, Mark Chang
-
Publication number: 20110276288Abstract: A system for analysing an interior energy system comprising: at least one detachable sensor arranged to monitor a portion of the interior energy system; and an apparatus comprising a processor configured to receive data of a first parameter of the interior energy system from the at least one detachable sensor and determine a second parameter of the interior energy which is inferred on the basis of the received data of the first parameter; and determine a characteristic of the interior energy system from the determined second parameter. The system may provide analysis of the interior energy system and recommend improvements.Type: ApplicationFiled: October 26, 2009Publication date: November 10, 2011Inventors: Mark Chang-Ming Hsieh, David Russell Anderson
-
Patent number: 8035153Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: GrantFiled: May 26, 2010Date of Patent: October 11, 2011Assignee: Spansion LLCInventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillip Jones, Mark Chang, Minh-Van Ngo
-
Publication number: 20110048729Abstract: The present disclosure provides an improved design for a pull tube sleeved stress joint and associated pull tube for managing stresses on a catenary riser for a floating offshore structure. The pull tube sleeve stress joint includes at least one sleeve surrounding a length of the pull tube with an annular gap between the sleeve and pull tube and a link ring therebetween. For embodiments having a plurality of sleeves, a first sleeve can be spaced by an annular first gap from the pull tube and coupled thereto with a first ring between the pull tube and the first sleeve, and a second sleeve can be spaced by an annular second gap from the first sleeve and coupled thereto with a second ring between the first sleeve and the second sleeve. Both pull tube and sleeves can be made with regular pipe segments welded together with regular girth welds.Type: ApplicationFiled: August 25, 2009Publication date: March 3, 2011Applicant: TECHNIP FRANCEInventors: Michael Y.H. LUO, Bob Lixin ZHANG, Shih-Hsiao Mark CHANG
-
Publication number: 20100230743Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: ApplicationFiled: May 26, 2010Publication date: September 16, 2010Inventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillip Jones, Mark Chang, Minh-Van Ngo
-
Patent number: 7732276Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: GrantFiled: April 26, 2007Date of Patent: June 8, 2010Assignee: Spansion LLCInventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillip Jones, Mark Chang, Minh-Van Ngo
-
Publication number: 20100099249Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.Type: ApplicationFiled: December 22, 2009Publication date: April 22, 2010Applicant: SPANSION LLCInventors: Kyunghoon Min, Angela Hui, Hiroyuki Kinoshita, Ning Cheng, Mark Chang
-
Patent number: 7691751Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.Type: GrantFiled: October 26, 2007Date of Patent: April 6, 2010Assignee: Spansion LLCInventors: Kyunghoon Min, Angela Hui, Hiroyuki Kinoshita, Ning Cheng, Mark Chang
-
Patent number: 7622389Abstract: A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.Type: GrantFiled: April 25, 2006Date of Patent: November 24, 2009Assignee: Spansion LLCInventors: Kyunghoon Min, Mark Chang, Ning Cheng, Brian Osborn, Kevin Song, Fei Wang, Angela Hui, Hiroyuki Kinoshita, Kuo-Tung Chang
-
Publication number: 20090111265Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.Type: ApplicationFiled: October 26, 2007Publication date: April 30, 2009Applicant: Spansion LLCInventors: Kyunghoon Min, Angela Hui, Hiroyuki Kinoshita, Ning Cheng, Mark Chang
-
Publication number: 20080265301Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.Type: ApplicationFiled: April 26, 2007Publication date: October 30, 2008Inventors: Shenqing Fang, Jihwan Choi, Calvin Gabriel, Fei Wang, Angela Hui, Alexander Nickel, Zubin Patel, Phillips Jones, Mark Chang, Minh-Van Ngo
-
Publication number: 20080061359Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.Type: ApplicationFiled: February 5, 2007Publication date: March 13, 2008Inventors: Chungho Lee, Hiroyuki Kinoshita, Zoran Krivokapic, Wei Zheng, Mark Chang, Rinji Sugino, Chi Chang
-
Patent number: 7256141Abstract: A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer of polycrystalline silicon formed on a surface of the interface layer.Type: GrantFiled: May 24, 2005Date of Patent: August 14, 2007Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Mark T. Ramsbey, Weidong Qian, Mark Chang, Eric Paton