Abstract: Current in a switching converter is controlled using a current-mode hysteretic controller. The high-side switch (usually a PMOS) is turned off when the current in the coil exceeds a certain peak control current. The low-side switch (usually an NMOS) is turned off when the current in the coil falls below a certain valley control current. A current ramp is added to one of these control currents, either peak or valley. The current ramp is initiated by a reference clock signal, which has the effect of synchronizing the switching converter to the reference clock.

Abstract: A variable efficiency and response buck converter is achieved. The device includes a multi-phase switch, the coupled coils, the filter capacitor, and the load. The multi-phase switch includes the phase control inputs, the circuit common reference, at least two pairs of complementary switches with each switch containing one upper switch and one lower switch, at least two phase control outputs from the complementary switches. The coupled inductive coils are coupled to the phase control outputs to enable weak couplings and strong couplings. Based on the working mode, equivalently the coupled coils can provide strong mutual inductances and weak mutual inductances. The filter capacitors connected to the output of the coupled coils provide high efficiency output to the load.

Abstract: A DC-DC switching converter is described, with a high magnetic coupling ratio between coils connected directly to a supply and ground, and with pass-device switches connected directly to an output. The pass-device switches are driven in such a way that the coils are magnetized alternately. The DC-DC switching converter may use multiple output switches, to supply multiple outputs. The DC-DC switching converter may use different turns-ratio on the coils, to adjust the duty-cycle of the switching converter operates, for a given supply voltage to output voltage ratio.

Abstract: The disclosure describes a DC-DC switching converter providing a peak-current servo, employing a pulse-frequency modulation (PFM) control signal and a constant on-time. A Buck, Boost, Buck-Boost, or similar switching converter that supports PFM mode is required, using a fixed on-time scheme for PFM. A final value of the coil current is sampled, and the sampled value of the coil current is compared to a target value for the coil current, to establish whether it is greater or less than the target value. The on-time of the high side device is adjusted to bring the final value of the coil current closer to the target value, using an adaptive coil current measurement.

Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of Operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.

Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of Operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.

Abstract: A switching mode power supply (SMPS) configured for clearing an overvoltage condition. The overvoltage is determined by detecting that the output voltage has exceeded the input voltage by a limited amount. The overvoltage is cleared by repetitively turning on and then off the switches controlling the flow of energy to the SMPS in sequence until the excess charge resulting from the overvoltage is couple to circuit ground, and the output is reduced to within acceptable limits.

Abstract: A servo block in a Buck, Boost, or switching converter allows a positive offset to be applied to the DAC voltage. In a typical switching converter application, the load will have a positive current, sourced from the switching converter to ground through the load. This will cause the output voltage of the switching converter to fall with the output impedance. The servo block corrects the output voltage by adjusting the DAC voltage upwards. In the case where current is forced back into the switching converter, causing the output voltage to rise, the servo block will have affect. The behavior of the servo block is desirable as it reduces the negative affect the servo block may have on load transients occurring when the switching converter is in over voltage. In particular, the idea of shifting the DAC voltage for several different loops with a single servo block is disclosed.

Abstract: The disclosure describes a DC-DC switching converter providing a peak-current servo, employing a pulse-frequency modulation (PFM) control signal and a constant on-time. A Buck, Boost, Buck-Boost, or similar switching converter that supports PFM mode is required, using a fixed on-time scheme for PFM. A final value of the coil current is sampled, and the sampled value of the coil current is compared to a target value for the coil current, to establish whether it is greater or less than the target value. The on-time of the high side device is adjusted to bring the final value of the coil current closer to the target value, using an adaptive coil current measurement.

Abstract: A DC-DC current-control mode switching converter is disclosed, with peak-mode control circuitry, configured to compare a coil current to a variable current limit, to turn off a high side device when the coil current exceeds the variable current limit. The DC-DC switching converter includes a compensation ramp generator, configured to provide a compensation ramp signal, and an offset circuit, configured to provide an offset current. The DC-DC switching converter further includes an amplifier, configured to generate a control current proportional to the difference between an output voltage and a target voltage, and an adder, to combine the control current, the compensation ramp signal, and the offset current. A DC-DC current-control mode switching converter, with valley-mode control circuitry, configured to compare a coil current to a variable current limit, to turn off a low side device when the coil current falls below the variable current limit, is also disclosed.

Abstract: A system is disclosed which allows for a multiphase Buck switching converter, where some phases operate in peak-mode current control, and some phases operate in valley-mode current control, simultaneously with the peak-mode phases. The peak-mode phases of the switching converter operate at lower frequency, and with a higher value inductor than the valley mode phases. The peak-mode phases support discontinuous control mode (DCM) operation and continuous control mode (CCM) operation, and the valley-mode phases only support CCM operation. The peak-mode phases of the switching converter are always enabled, and the valley-mode phases are only enabled at high currents. The peak-mode and valley-mode currents are matched with a peak current servo, for better efficiency.

Abstract: The clock input of a buck converter is delayed, and the delay is controlled proportionally to the preceding high-side output switch on time. In the steady state, the high-side switch on time is uniform, and the clock is offset by a fixed amount. When sub-harmonic oscillation begins to occur, the high-side switch on time may increase during a cycle. The longer high-side on time causes the clock to be delayed by an increased amount. This has the effect of increasing the following low-side output switch on time. This further increases the subsequent high-side on time, and counteracts the effects of sub-harmonic oscillation. If the system is properly controlled, loop compensation is implemented correctly and sub-harmonic oscillation is prevented. In addition, the scheme may also be configured for the delay to be controlled proportionally to the preceding low-side output switch on time of the buck converter.

Abstract: A servo block in a Buck, Boost, or switching converter allows a positive offset to be applied to the DAC voltage. In a typical switching converter application, the load will have a positive current, sourced from the switching converter to ground through the load. This will cause the output voltage of the switching converter to fall with the output impedance. The servo block corrects the output voltage by adjusting the DAC voltage upwards. In the case where current is forced back into the switching converter, causing the output voltage to rise, the servo block will have affect. The behavior of the servo block is desirable as it reduces the negative affect the servo block may have on load transients occurring when the switching converter is in over voltage. In particular, the idea of shifting the DAC voltage for several different loops with a single servo block is disclosed.

Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.

Abstract: A buck converter device with minimum off-time operation, the device comprising a comparator providing an output signal of a minimum off time, a first amplifier, a p-channel MOSFET whose gate is connected to the output of a first amplifier providing a signal threshold voltage to a positive terminal of a comparator, a second amplifier; and, a second p-channel MOSFET whose gate is connected to the output of a second amplifier providing a signal to a negative terminal of a comparator, and a capacitor element. A capacitor establishes a voltage whose rate of change is proportional to power supply Vdd, establishing a time to charge the capacitor to a threshold voltage proportional to (Vdd?Vref)/Vdd, and establishing a minimum off time on the output of a comparator.

Abstract: A peak-current sampling circuit, with current emulation auto-calibration, is disclosed, to create a current-mode control scheme, in a DC-DC switching converter, operating at frequencies above where traditional current-mode control schemes fail. To accomplish this, a replica signal is created inside a switching converter that emulates the current in the coil. This internal signal can then be used to control the switching converter. This signal will not suffer the ringing and long settling times that affect the actual current signal. This signal can also have a much larger magnitude than the actual current signal, and can therefore trigger the comparator with less delay. This signal can then be auto-calibrated to ensure it matches the actual coil current of the DC-DC switching converter.

Abstract: The proposed disclosure combines peak-mode monitoring with valley-mode control, in a Buck switching converter, by means of a peak-current sampling circuit, not to turn the high side device off, but to control a slow loop, which in turn controls a variable offset incorporated into the loop control current. This helps the loop control current define the exact peak current, regardless of what other offsets, compensation ramp or peak-to-peak current ripple, are applied to the loop control current. The peak current is determined by an operational transconductance amplifier (OTA), whose maximum current is clamped to a programmed value. The loop control current is most likely implemented using a digital successive approximation register (SAR) system, but may also be implemented using a slow analog control loop.

Abstract: A system is disclosed which provides a dynamic current limit circuit that accurately defines both the lower and the upper limits for the current limit. The circuit ensures both the lower and upper current limits are well-controlled. The lower current limit is matched to the normal pulse-frequency modulation (PFM) limit, and the upper current limit is matched to the pulse-width modulation (PWM) limit. This implementation has several key benefits, including making the peak current limit accurate in both sync and dynamic sleep modes. If the scheme is carefully designed, the dynamic sleep current limit gives the best load transient response.

Abstract: A variable efficiency and response buck converter is achieved. The device includes a multi-phase switch, the coupled coils, the filter capacitor, and the load. The multi-phase switch includes the phase control inputs, the circuit common reference, at least two pairs of complementary switches with each switch containing one upper switch and one lower switch, at least two phase control outputs from the complementary switches. The coupled inductive coils are coupled to the phase control outputs to enable weak couplings and strong couplings. Based on the working mode, equivalently the coupled coils can provide strong mutual inductances and weak mutual inductances. The filter capacitors connected to the output of the coupled coils provide high efficiency output to the load.

Abstract: An average load current calculator circuit configured for determining an average load current within an at least one phase switch mode power converter (SMPC) having at least one peak/valley detector receives an inductor current sense signal and determines and holds a peak or valley amplitude of the inductor current sense signal. A current corrector circuit receives an input voltage and an output voltage of the SMPC and an inductance value of the inductor of the SMPC for determining an average correction current of the peak or valley amplitude of the current sense. An average current generator receives the peak or valley amplitude of the current sense signal and the average correction current for determining the instantaneous average load current within a switch mode power converter (SMPC) by additively combining the peak or valley amplitude of the current sense signal and the average correction current.