Patents by Inventor Mark D. Hummel

Mark D. Hummel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10248315
    Abstract: Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: April 2, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: David E. Mayhew, Mark D. Hummel, Michael J. Osborn
  • Patent number: 9535849
    Abstract: An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: January 3, 2017
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Andrew G. Kegel, Mark D. Hummel, Stephen D. Glaser
  • Patent number: 9424199
    Abstract: A virtual input/output memory management unit (IOMMU) is configured to provide a firewall around memory requests associated with an input/output (I/O) device. The virtual IOMMU uses data structures including a guest page table, a host page table and a general control register (i.e., GCR3) table. The guest page table is implemented in hardware to support the speed requirements of the virtual IOMMU. The GCR3 table is indexed using a virtual DeviceID parameter stored in a device table.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: August 23, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew G. Kegel, Mark D. Hummel
  • Patent number: 9251001
    Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: February 2, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Osborn, Mark D. Hummel, David E. Mayhew
  • Publication number: 20160004445
    Abstract: Described are aggregation devices and methods for interconnecting server nodes. The aggregation device can include an input region, an output region, and a memory switch. The input region includes a plurality of input ports. The memory switch has a shared through silicon via (TSV) memory coupled to the input ports for temporarily storing data received at the input ports from a plurality of source devices. The output region includes a plurality of output ports coupled to the TSV memory. The output ports provide the data to a plurality of destination devices. A memory allocation system coordinates a transfer of the data from the source devices to the TSV memory. The output ports receive and process the data from the TSV memory independently of a communication from the input ports.
    Type: Application
    Filed: September 14, 2015
    Publication date: January 7, 2016
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: David E. Mayhew, Mark D. Hummel, Michael J. Osborn
  • Publication number: 20150339192
    Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.
    Type: Application
    Filed: June 16, 2015
    Publication date: November 26, 2015
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Osborn, Mark D. Hummel, David E. Mayhew
  • Patent number: 9152571
    Abstract: An input/output memory management unit (IOMMU) having an “invalidate all” command available to clear the contents of cache memory is presented. The cache memory provides fast access to address translation data that has been previously obtained by a process. A typical cache memory includes device tables, page tables and interrupt remapping entries. Cache memory data can become stale or be compromised from security breaches or malfunctioning devices. In these circumstances, a rapid approach to clearing cache memory content is provided.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: October 6, 2015
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Andrew G. Kegel, Mark D. Hummel, Anthony Asaro
  • Patent number: 9069698
    Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: June 30, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Osborn, Mark D. Hummel, David E. Mayhew
  • Patent number: 9009419
    Abstract: Methods and systems are provided for mapping a memory instruction to a shared memory address space in a computer arrangement having a CPU and an APD. A method includes receiving a memory instruction that refers to an address in the shared memory address space, mapping the memory instruction based on the address to a memory resource associated with either the CPU or the APD, and performing the memory instruction based on the mapping.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 14, 2015
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark D. Hummel, Mark Fowler
  • Patent number: 8966461
    Abstract: A medium, method, and apparatus are disclosed for eliding superfluous function invocations in a vector-processing environment. A compiler receives program code comprising a width-contingent invocation of a function. The compiler creates a width-specific executable version of the program code by determining a vector width of a target computer system and omitting the function from the width-specific executable if the vector width meets one or more criteria. For example, the compiler may omit the function call if the vector width is greater than a minimum size.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: February 24, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benedict R. Gaster, Lee W. Howes, Mark D. Hummel
  • Patent number: 8929220
    Abstract: In a processing system comprising a plurality of processing nodes coupled via a switching fabric, a method includes implementing a flow control property for a data flow in the switching fabric based on an addressing property of an address of a virtual network interface controller associated with the data flow. A switching fabric includes a plurality of ports, each port coupleable to a corresponding processing node, and switching logic coupled to the plurality of ports. The switching fabric further includes flow control logic to implement a flow control property for a data flow in the switching logic based on an addressing property of an address of a virtual network interface controller associated with the data flow.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: January 6, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Jr., Anton Chernoff, Mark D. Hummel
  • Patent number: 8706941
    Abstract: In an embodiment, a device interrupt manager may be configured to receive an interrupt from a device that is assigned to a guest. The device interrupt manager may be configured to transmit an operation targeted to a memory location in a system memory to record the interrupt for a virtual processor within the guest, wherein the interrupt is to be delivered to the targeted virtual processor. In an embodiment, a virtual machine manager may be configured to detect that an interrupt has been recorded by the device interrupt manager for a virtual processor that is not currently executing. The virtual machine manager may be configured to schedule the virtual processor for execution on a hardware processor, or may prioritize the virtual processor for scheduling, in response to the interrupt.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: April 22, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin C. Serebrin, Rodney W. Schmidt, David A. Kaplan, Mark D. Hummel
  • Publication number: 20140068137
    Abstract: A virtual input/output memory management unit (IOMMU) is configured to provide a firewall around memory requests associated with an input/output (I/O) device. The virtual IOMMU uses data structures including a guest page table, a host page table and a general control register (i.e., GCR3) table. The guest page table is implemented in hardware to support the speed requirements of the virtual IOMMU. The GCR3 table is indexed using a virtual DeviceID parameter stored in a device table.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Inventors: Andrew G. Kegel, Mark D. Hummel
  • Publication number: 20140068139
    Abstract: A system includes: a memory controller; a memory module with memory blocks in communication with the memory controller; an input controller in communication with the memory controller, where the memory controller notifies the input controller of a Next Address To Write corresponding with a Next Memory Block To Write in the memory module, each input block contains an address to a next block, and data is written to the is Memory Block To Write at the Next Address To Write in the memory module; and an output controller in communication with the other controllers, receives a starting address from the input controller of a first memory block to read from the memory module, a starting address is a Next Address To Read from a Next Memory Block To Read in the memory module, and the memory controller compares the Next Address To Write with the Next Address To Read.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Osborn, Mark D. Hummel, David E. Mayhew
  • Publication number: 20140068373
    Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Osborn, Mark D. Hummel, David E. Mayhew
  • Publication number: 20140068220
    Abstract: A hardware based memory allocation system in a computer includes: a memory module formatted with memory blocks; an input controller, in communications with the memory module and receiving a transfer request from a requestor, for transferring data from a source to the memory module; an output controller, in communications with the memory module and the input controller, for transferring data from the memory module to a destination; and a block allocator, in communications the input controller and the output controller, for maintaining a Block Descriptor Index (BDI) of Free List (FL) Addresses, each FL address pointing to a Block Descriptor Page (BDP) having a plurality of Memory Block (MB) addresses, each MB address pointing to a free memory block in the memory module.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Osborn, David E. Mayhew, Mark D. Hummel
  • Publication number: 20140056141
    Abstract: In a processing system comprising a plurality of processing nodes coupled via a switching fabric, a method includes implementing a flow control property for a data flow in the switching fabric based on an addressing property of an address of a virtual network interface controller associated with the data flow. A switching fabric includes a plurality of ports, each port coupleable to a corresponding processing node, and switching logic coupled to the plurality of ports. The switching fabric further includes flow control logic to implement a flow control property for a data flow in the switching logic based on an addressing property of an address of a virtual network interface controller associated with the data flow.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, JR., Anton Chernoff, Mark D. Hummel
  • Patent number: 8661177
    Abstract: A method and apparatus are provided for controlling system management interrupts is disclosed. An interrupt filter comprises a memory, a comparator and a logic circuit. The memory is adapted to contain a list indicating one or more devices with permission associated with an interrupt signal. The comparator is adapted to receive an interrupt signal containing type information from the one or more devices. The comparator is adapted to compare the interrupt type against the list to determine if the one or more devices is permitted to send the interrupt signal. The logic circuit blocks or passes the interrupt signal in response to the result of the comparison.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: February 25, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew G. Kegel, Mark D. Hummel
  • Publication number: 20140040560
    Abstract: An input/output memory management unit (IOMMU) having an “invalidate all” command available to clear the contents of cache memory is presented. The cache memory provides fast access to address translation data that has been previously obtained by a process. A typical cache memory includes device tables, page tables and interrupt remapping entries. Cache memory data can become stale or be compromised from security breaches or malfunctioning devices. In these circumstances, a rapid approach to clearing cache memory content is provided.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: Andrew G. Kegel, Mark D. Hummel, Anthony Asaro
  • Publication number: 20140040565
    Abstract: Methods and systems are provided for mapping a memory instruction to a shared memory address space in a computer arrangement having a CPU and an APD. A method includes receiving a memory instruction that refers to an address in the shared memory address space, mapping the memory instruction based on the address to a memory resource associated with either the CPU or the APD, and performing the memory instruction based on the mapping.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: Anthony ASARO, Kevin NORMOYLE, Mark D. HUMMEL, Mark FOWLER