Abstract: Nanoparticle-fibrous membrane composites are provided as tunable interfacial scaffolds for flexible chemical sensors and biosensors by assembling gold nanoparticles (Au NPs) in a fibrous membrane. The gold nanoparticles are functionalized with organic, polymeric and/or biological molecules. The fibrous membranes may include different filter papers, with one example featuring a multilayered fibrous membrane consisting of a cellulose nanofiber (CN) top layer, an electrospun polyacrylonitrile (PAN) nanofibrous midlayer (or alternate material), and a non-woven polyethylene terephthalate (PET) fibrous support layer, with the nanoparticles provided on the fibrous membranes through interparticle molecular/polymeric linkages and nanoparticle-nanofibrous interactions. Molecular linkers may be employed to tune hydrogen bonding and electrostatic and/or hydrophobic/hydrophilic interactions to provide sensor specificity to gases or liquids. The sensors act as chemiresistor-type sensors.

Abstract: Nanoparticle-fibrous membrane composites are provided as tunable interfacial scaffolds for flexible chemical sensors and biosensors by assembling gold nanoparticles (Au NPs) in a fibrous membrane. The gold nanoparticles are functionalized with organic, polymeric and/or biological molecules. The fibrous membranes may include different filter papers, with one example featuring a multilayered fibrous membrane consisting of a cellulose nanofiber (CN) top layer, an electrospun polyacrylonitrile (PAN) nanofibrous midlayer (or alternate material), and a nonwoven polyethylene terephthalate (PET) fibrous support layer, with the nanoparticles provided on the fibrous membranes through interparticle molecular/polymeric linkages and nanoparticle-nanofibrous interactions. Molecular linkers may be employed to tune hydrogen bonding and electrostatic and/or hydrophobic/hydrophilic interactions to provide sensor specificity to gases or liquids. The sensors act as chemiresistor-type sensors.

Abstract: Nanoparticle-fibrous membrane composites are provided as tunable interfacial scaffolds for flexible chemical sensors and biosensors by assembling gold nanoparticles (Au NPs) in a fibrous membrane. The gold nanoparticles are functionalized with organic, polymeric and/or biological molecules. The fibrous membranes may include different filter papers, with one example featuring a multilayered fibrous membrane consisting of a cellulose nanofiber (CN) top layer, an electrospun polyacrylonitrile (PAN) nanofibrous midlayer (or alternate material), and a nonwoven polyethylene terephthalate (PET) fibrous support layer, with the nanoparticles provided on the fibrous membranes through interparticle molecular/polymeric linkages and nanoparticle-nanofibrous interactions. Molecular linkers may be employed to tune hydrogen bonding and electrostatic and/or hydrophobic/hydrophilic interactions to provide sensor specificity to gases or liquids. The sensors act as chemiresistor-type sensors.

Abstract: A method for forming a film on a conductive substrate, comprising immersing a substrate having a conductive portion in a solution comprising a metal ion ceramic precursor for the film and a peroxide; applying a voltage potential to the conductive portion with respect to a counter electrode in the solution, sufficient to protect the conductive portion from corrosion by the solution, and drive formation of a film on the substrate, controlling a pH of the solution while limiting a production of hydrogen by electrolysis of the solution proximate to the conductive portion; and maintaining the voltage potential for a sufficient duration to produce a film on the conductive portion. An electrode may be formed over the film to produce an electrical device. The film may be, for example, insulating, dielectric, resistive, semiconductive, magnetic, or ferromagnetic.

Abstract: A system and method for imaging gamma- and x-ray, and charged particles sources employing a three dimensional array of scintillation elements arranged surrounding an emission source. According to a preferred embodiment, each element of the array comprises a scintillator element, a solid-state photon detector, and processing electronics to output an electronic signal. The elements may be efficiently packed in both the X-Y plane and stacked in the Z-axis, to provide depth of interaction information. The elements of the array are preferably hierarchically arranged with control electronics provided together for subarray modules (e.g., an n×m×1 module), and synchronization electronics provided at a larger scale. The modules preferably communicate with a control system through a shared addressable packet switched digital communication network with a control and imaging system, and receive control information from that system through the network.

Abstract: A system and method for imaging gamma- and x-ray, and charged particles sources employing a three dimensional array of scintillation elements arranged surrounding an emission source. According to a preferred embodiment, each element of the array comprises a scintillator element, a solid-state photon detector, and processing electronics to output an electronic signal. The elements may be efficiently packed in both the X-Y plane and stacked in the Z-axis, to provide depth of interaction information. The elements of the array are preferably hierarchically arranged with control electronics provided together for subarray modules (e.g., an n×m×1 module), and synchronization electronics provided at a larger scale. The modules preferably communicate with a control system through a shared addressable packet switched digital communication network with a control and imaging system, and receive control information from that system through the network.

Abstract: A method for forming a film on a conductive substrate, comprising immersing a substrate having a conductive portion in a solution comprising a metal ion ceramic precursor for the film and a peroxide; applying a voltage potential to the conductive portion with respect to a counter electrode in the solution, sufficient to protect the conductive portion from corrosion by the solution, and drive formation of a film on the substrate, controlling a pH of the solution while limiting a production of hydrogen by electrolysis of the solution proximate to the conductive portion; and maintaining the voltage potential for a sufficient duration to produce a film on the conductive portion. An electrode may be formed over the film to produce an electrical device. The film may be, for example, insulating, dielectric, resistive, semiconductive, magnetic, or ferromagnetic.

Abstract: A method for forming a film on a conductive substrate, comprising immersing a substrate having a conductive portion in a solution comprising a metal ion ceramic precursor for the film and a peroxide; applying a voltage potential to the conductive portion with respect to a counter electrode in the solution, sufficient to protect the conductive portion from corrosion by the solution, and drive formation of a film on the substrate, controlling a pH of the solution while limiting a production of hydrogen by electrolysis of the solution proximate to the conductive portion; and maintaining the voltage potential for a sufficient duration to produce a film on the conductive portion. An electrode may be formed over the film to produce an electrical device. The film may be, for example, insulating, dielectric, resistive, semiconductive, magnetic, or ferromagnetic.

Abstract: A method for forming a film on a conductive substrate, comprising immersing a substrate having a conductive portion in a solution comprising a metal ion ceramic precursor for the film and a peroxide; applying a voltage potential to the conductive portion with respect to a counter electrode in the solution, sufficient to protect the conductive portion from corrosion by the solution, and drive formation of a film on the substrate, controlling a pH of the solution while limiting a production of hydrogen by electrolysis of the solution proximate to the conductive portion; and maintaining the voltage potential for a sufficient duration to produce a film on the conductive portion. An electrode may be formed over the film to produce an electrical device. The film may be, for example, insulating, dielectric, resistive, semiconductive, magnetic, or ferromagnetic.

Abstract: A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.

Abstract: A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

Abstract: A method of forming a circuitized substrate for use in electronic packages. A substrate layer is provided that has a copper pad on a surface. A conductive seed layer and a photoresist layer are placed on the surface. The photoresist is developed and conductive material is placed within the developed features and a second conductive material placed on the first conductive material. The photoresist and conductive seed layer are removed to leave a micro-pillar array. The joining and lamination of two circuitized substrate layers utilizes the micro-pillar array for the electrical connection of the circuitized substrate layers.

Abstract: A circuitized substrate for use in such electrical structures as information handling systems wherein the substrate includes a capacitive substrate as part thereof. The capacitive substrate includes a thin film layer of capacitive material strategically positioned on a conductive layer relative to added electrically conductive elements to in turn provide a plurality of internal capacitors within the final circuitized substrate during operation thereof. A method of making such a circuitized substrate is also provided.

Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.

Abstract: A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

Abstract: A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.

Abstract: A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.