Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract: A multi-layered structure and method of formation. A page is generated by stacking N substructures (N≧2) in an ordered sequence. A first substructure of each pair of adjacent substructures comprises liquid crystal polymer (LCP) dielectric material to be bonded with a second substructure of a pair of the adjacent substructure. The page is subjected to a temperature less than the lowest nematic-to-isotropic transition temperature of the LCP dielectric materials within the page. The dwell time and elevated pressure are sufficient to cause all LCP dielectric material within the page to plastically deform and laminate each pair of adjacent substructures without any extrinsic adhesive layer disposed between the first and second substructures of each pair of adjacent substructures.

Abstract: A structure and method for forming a tamper respondent electronic circuit enclosure that includes an integrated circuit structure, a mesh structure surrounding the integrated circuit structure, and a sealed enclosure surrounding the mesh structure. The mesh structure includes a layer of flexible dielectric having a first side and a second side, a screen-printed pattern of flexible electrically conductive first circuit lines forming a first resistor network on the first side, and a photo lithographically-formed pattern of flexible electrically conductive second circuit lines forming a second resistor network on the second side.

Abstract: Conductive materials that have low coefficients of thermal expansion (CTEs) and that are used for power and ground planes are disclosed. Fibrous materials (such as carbon, graphite, glass, quartz, polyethylene, and liquid crystal polymer fibers) with low CTEs are metallized to provide a resultant conductive material with a low CTE. Such fibers may be metallized in their individual state and then formed into a fabric, or these materials may be formed into a fabric and then metallized or a combination of both metallizations may be used. In addition, a graphite or carbon sheet may be metallized on one or both sides to provide a material that has a low CTE and high conductivity. These metallized, low CTE power and ground planes may be laminated with other planes/cores into a composite, or laminated into a core which is then laminated with other planes/cores into a composite. The resultant composite may be used for printed circuit boards (PCBs) or PCBs used as laminate chip carriers.

Abstract: A multi-layered structure and method of formation. A page is generated by stacking N substructures (N≧2) in an ordered sequence. A first substructure of each pair of adjacent substructures comprises liquid crystal polymer (LCP) dielectric material to be bonded with a second substructure of a pair of the adjacent substructure. The page is subjected to a temperature less than the lowest nematic-to-isotropic transition temperature of the LCP dielectric materials within the page. The dwell time and elevated pressure are sufficient to cause all LCP dielectric material within the page to plastically deform and laminate each pair of adjacent substructures without any extrinsic adhesive layer disposed between the first and second substructures of each pair of adjacent substructures.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: A structure and method for forming a tamper respondent electronic circuit enclosure that includes an integrated circuit structure, a mesh structure surrounding the integrated circuit structure, and a sealed enclosure surrounding the mesh structure. The mesh structure includes a layer of flexible dielectric having a first side and a second side, a screen-printed pattern of flexible electrically conductive first circuit lines forming a first resistor network on the first side, and a photo lithographically-formed pattern of flexible electrically conductive second circuit lines forming a second resistor network on the second side.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: Power and ground planes that are used in Printed Circuit Boards (PCBs) and that comprise porous, conductive materials are disclosed. Using porous power and ground plane materials in PCBs allows liquids (e.g., water and/or other solvents) to pass through the power and ground planes, thus decreasing failures in PCBs (or PCBs used as laminate chip carriers) caused by cathodic/anodic filament growth and delamination of insulators. Porous conductive materials suitable for use in PCBs may be formed by using metal-coated organic cloths (such as polyester or liquid crystal polymers) or fabrics (such as those made from carbon/graphite or glass fibers), using metal wire mesh instead of metal sheets, using sintered metal, or making metal sheets porous by forming an array of holes in the metal sheets. Fabrics and mesh may be woven or random. If an array of holes is formed in a metal sheet, such an array may be formed with no additional processing steps than are performed using conventional PCB assembly methods.

Abstract: Power and ground planes used in Printed Circuit Boards (PCBs) having porous, conductive materials allow liquids (e.g., water and/or other solvents) to pass through the power and ground planes, thus decreasing failures in PCBs (or PCBs used as laminate chip carriers) caused by cathodic/anodic filament growth and delamination of insulators. Porous conductive materials suitable for use in PCBs may be formed by using metal-coated organic cloths (such as polyester or liquid crystal polymers) or fabrics (such as those made from carbon/graphite or glass fibers), using metal wire mesh instead of metal sheets, using sintered metal, or making metal sheets porous by forming an array of holes in the metal sheets. Fabrics and mesh may be woven or random. If an array of holes is formed in a metal sheet, such an array may be formed with no additional processing steps than are performed using conventional PCB assembly methods.

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract: An electronic interconnection assembly having a thin film bonded to either a glass ceramic or to an organic laminate substrate, and a method for attaching a thin film wiring package to the substrate. Provided is the utilization of adhesives which may be processed at significantly lower temperatures so as to avoid damaging components, the wiring package and interconnection joints. Moreover, pursuant to specific aspects, the joining of the thin film to the substrate may be implemented with the utilization of dendrites.

Abstract: A halogen-free dielectric resin mixture is described for use in microvia and other similar applications. The resin mixture contains a cyanate ester monomer or prepolymer a bismaleimide, an epoxy and a flame inhibiting compound selected from the group consisting of a phosphinic acid anhydride, a phosphonic acid andydride and a phosphonic acid half-ester. The flame inhibitor is present in an amount wherein the elemental phosphorus content is between about 2% and about 20% by weight, based on the weight of the resin mixture. The resin mixture can also include one or more coloring, fluorescent and UV absorbing agents. Prepregs based on the resin mixture with inorganic or organic reinforcing agents, as well as circuit boards and chip carriers made from the prepregs are also described. A resin coated article for use in microvia laser applications is likewise included.

Abstract: A semiconductor device having a thermoset-containing, dielectric material and methods for fabricating the same is provided. The device may take the form of a printed circuit board, an integrated circuit chip carrier, or the like. The dielectric material is a non-fibrillated, fluoropolymer matrix that has inorganic particles distributed therein and is impregnated with a thermoset material.

Abstract: A method of forming a laminated composite printed wiring structure of a plurality of at least three superimposed subcomposites having organic substrates is provided. Via openings in the subcomposite structures having conductive paste therein are positioned to align with openings in at least one adjacent subcomposite structure also filled with conductive paste that is to be joined thereto. Printed wiring is provided on at least one face of one subcomposite structure. A fixture with pins which extends through index openings in the composites are provided to mount masks for screening paste and stacking of the composites is provided. After screening of paste, and partially curing of the paste, in each composite, a group of composites is placed on the fixture and the pastes are fully cured to form a unitary structure.

Abstract: A halogen-free dielectric resin mixture is described for use in microvia and other similar applications. The resin mixture contains a cyanate ester monomer or prepolymer a bismaleimide, an epoxy and a flame inhibiting compound selected from the group consisting of a phosphinic acid anhydride, a phosphonic acid andydride and a phosphonic acid half-ester. The flame inhibitor is present in an amount wherein the elemental phosphorus content is between about 2% and about 20% by weight, based on the weight of the resin mixture. The resin mixture can also include one or more coloring, fluorescent and UV absorbing agents. Prepregs based on the resin mixture with inorganic or organic reinforcing agents, as well as circuit boards and chip carriers made from the prepregs are also described. A resin coated article for use in microvia laser applications is likewise included.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: A structure and method for forming a tamper respondent electronic circuit enclosure that includes an integrated circuit structure, a mesh structure surrounding the integrated circuit structure, and a sealed enclosure surrounding the mesh structure. The mesh structure includes a layer of flexible dielectric having a first side and a second side, a screen-printed pattern of flexible electrically conductive first circuit lines forming a first resistor network on the first side, and a photo lithographically-formed pattern of flexible electrically conductive second circuit lines forming a second resistor network on the second side.