Patents by Inventor Mark D. Smith

Mark D. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250103019
    Abstract: A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Franz Zach, Mark D. Smith, Roel Gronheid
  • Publication number: 20250104216
    Abstract: Based on an initial probability of occurrence of a stochastic defect over a layout of a workpiece, a subset of locations on the workpiece are selected where the initial probability is above a threshold. The subset of locations are grouped by pattern shapes. An expected defect count is determined for each of the pattern shapes. A subset of the pattern shapes is then selected for repair.
    Type: Application
    Filed: September 24, 2024
    Publication date: March 27, 2025
    Inventors: Pradeep Vukkadala, Cao Zhang, Anatoly Burov, Guy Parsey, Kyeongeun Ko, Sergei G. Bakarian, Janez Krek, Kunlun Bai, Craig Higgins, John S. Graves, Mark D. Smith, John Biafore
  • Publication number: 20250104214
    Abstract: Using an initial probability of occurrence of a stochastic defect over an inspection area of a workpiece, one or more defects within the inspection area are imaged using an optical tool or an electron beam tool. A probability of occurrence of a stochastic defect at each of the defect locations is generated using the model. The defect locations are grouped into probability bins. A consistency between the initial probability and observed results is determined and the model can be tuned based on the consistency.
    Type: Application
    Filed: September 24, 2024
    Publication date: March 27, 2025
    Inventors: Pradeep Vukkadala, Cao Zhang, Anatoly Burov, Guy Parsey, Kyeongeun Ko, Sergei G. Bakarian, Janez Krek, Kunlun Bai, Craig Higgins, John S. Graves, Mark D. Smith, John J. Biafore
  • Publication number: 20250104215
    Abstract: An initial probability of occurrence of a stochastic defect over an inspection area of a workpiece is received. All locations of the stochastic defects are sorted by the initial probability of occurrence. A cumulative expected defect count is determined and the cumulative expected defect count is normalized to be a fraction of a total expected defect count. A number of defect locations is determined to capture potential stochastic defects above a threshold of total stochastic defects.
    Type: Application
    Filed: September 24, 2024
    Publication date: March 27, 2025
    Inventors: Pradeep Vukkadala, Cao Zhang, Anatoly Burov, Guy Parsey, Kyeongeun Ko, Sergei G. Bakarian, Janez Krek, Kunlun Bai, Craig Higgins, John S. Graves, Mark D. Smith, John J. Biafore
  • Publication number: 20250035489
    Abstract: Metrology methods, modules and targets are provided, for measuring tilted device designs. The methods analyze and optimize target design with respect to the relation of the Zernike sensitivity of pattern placement errors (PPEs) between target candidates and device designs. Monte Carlo methods may be applied to enhance the robustness of the selected target candidates to variation in lens aberration and/or in device designs. Moreover, considerations are provided for modifying target parameters judiciously with respect to the Zernike sensitivities to improve metrology measurement quality and reduce inaccuracies.
    Type: Application
    Filed: October 14, 2024
    Publication date: January 30, 2025
    Inventors: Myungjun Lee, Mark D. Smith, Michael E. Adel, Eran Amit, Daniel Kandel
  • Patent number: 12197137
    Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: January 14, 2025
    Assignee: KLA Corporation
    Inventors: Franz Zach, Mark D. Smith, Xiaomeng Shen, Jason Saito, David Owen
  • Patent number: 12164277
    Abstract: A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.
    Type: Grant
    Filed: October 9, 2023
    Date of Patent: December 10, 2024
    Assignee: KLA Corporation
    Inventors: Franz Zach, Mark D. Smith, Roel Gronheid
  • Patent number: 12117347
    Abstract: Metrology methods, modules and targets are provided, for measuring tilted device designs. The methods analyze and optimize target design with respect to the relation of the Zernike sensitivity of pattern placement errors (PPEs) between target candidates and device designs. Monte Carlo methods may be applied to enhance the robustness of the selected target candidates to variation in lens aberration and/or in device designs. Moreover, considerations are provided for modifying target parameters judiciously with respect to the Zernike sensitivities to improve metrology measurement quality and reduce inaccuracies.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: October 15, 2024
    Assignee: KLA Corporation
    Inventors: Myungjun Lee, Mark D. Smith, Michael E. Adel, Eran Amit, Daniel Kandel
  • Publication number: 20240120186
    Abstract: Plasma parameters at a surface of a wafer are determined with a plasma hypermodel based on plasma processing conditions. A post-processing profile can be predicted for the surface of the wafer with a feature-scale profile model. Correlations in the plasma hypermodel can be recalibrated if the post-processing profile is outside a convergence criterion of an experimental reference.
    Type: Application
    Filed: November 7, 2022
    Publication date: April 11, 2024
    Inventors: Chad HUARD, Premkumar PANNEERCHELVAM, Shuo HUANG, Mark D. SMITH
  • Publication number: 20240094642
    Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Franz Zach, Mark D. Smith, Xiaomeng Shen, Jason Saito, David Owen
  • Publication number: 20240053721
    Abstract: A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.
    Type: Application
    Filed: October 9, 2023
    Publication date: February 15, 2024
    Inventors: Franz Zach, Mark D. Smith, Roel Gronheid
  • Patent number: 11829077
    Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 28, 2023
    Assignee: KLA Corporation
    Inventors: Franz Zach, Mark D. Smith, Xiaomeng Shen, Jason Saito, David Owen
  • Patent number: 11782411
    Abstract: A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: October 10, 2023
    Assignee: KLA Corporation
    Inventors: Franz Zach, Mark D. Smith, Roel Gronheid
  • Patent number: 11682570
    Abstract: A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: June 20, 2023
    Assignee: KLA Corporation
    Inventors: Pradeep Vukkadala, Mark D. Smith, Ady Levy, Prasanna Dighe, Dieter Mueller
  • Publication number: 20230032406
    Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a bonded pair of wafers, where the bonded pair of wafers are bonded with a bonding tool. The wafer shape metrology sub-system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; convert the stress-free shape measurements into an overlay distortion pattern; detect one or more localized deviations in the bonded pair of wafers in order to identify one or more contaminant particles on the bonding tool; and report the one or more localized deviations in the bonded pair of wafers.
    Type: Application
    Filed: January 31, 2022
    Publication date: February 2, 2023
    Inventors: Franz Zach, Mark D. Smith, Roel Gronheid
  • Publication number: 20230035201
    Abstract: A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.
    Type: Application
    Filed: January 31, 2022
    Publication date: February 2, 2023
    Inventors: Franz Zach, Mark D. Smith, Roel Gronheid
  • Publication number: 20230030116
    Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform stress-free shape measurements on an active wafer, a carrier wafer, and a bonded device wafer. The active wafer includes functioning logic circuitry and the carrier wafer is electrically passive. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements; determine overlay distortion between features on the active wafer and the carrier wafer; and convert the overlay distortion to a feed-forward correction for one or more lithographic scanners. The controller is also configured to determine a control range for a bonder or lithography scanner; predict an overlay distortion pattern; calculate an optimal control signature based on a minimal achievable overlay; and provide a feed-forward correction to the bonder or lithography scanner based on the calculated optimal control signature.
    Type: Application
    Filed: January 31, 2022
    Publication date: February 2, 2023
    Inventors: Franz Zach, Mark D. Smith, Roel Gronheid
  • Publication number: 20220187718
    Abstract: A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 16, 2022
    Applicant: KLA Corporation
    Inventors: Franz Zach, Mark D. Smith, Xiaomeng Shen, Jason Saito, David Owen
  • Patent number: 11221561
    Abstract: An overlay control system is disclosed. In embodiments, the system may include a controller configured to: acquire a set of feedback overlay measurements based on a plan of record (POR) sampling map on a second layer of samples of at least one previous lot of samples; generate a reference wafer overlay map based on the set of feedback overlay measurements; acquire a set of feedforward overlay measurements based on a feedforward sampling map on a first layer of a set of samples of a current lot of samples; generate a set of artificial overlay vector maps for the set of samples of the current lot of samples based on the set of feedforward overlay measurements; and cause a lithography tool to fabricate a second layer of samples of the current lot of samples based on the reference wafer overlay map and the set of artificial overlay vector maps.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: January 11, 2022
    Assignee: KLA Corporation
    Inventors: Onur Nihat Demirer, Fatima Anis, Mark D. Smith
  • Publication number: 20220005714
    Abstract: A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.
    Type: Application
    Filed: September 20, 2021
    Publication date: January 6, 2022
    Inventors: Pradeep Vukkadala, Mark D. Smith, Ady Levy, Prasanna Dighe, Dieter Mueller