Patents by Inventor Mark David Werkheiser

Mark David Werkheiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220164288
    Abstract: Entries in a cluster-to-caching agent map table of a data processing network identify one or more caching agents in a caching agent cluster. A snoop filter cache stores coherency information that includes coherency status information and a presence vector, where a bit position in the presence vector is associated with a caching agent cluster in the cluster-to-caching agent map table. In response to a data request, a presence vector in the snoop filter cache is accessed to identify a caching agent cluster and the map table is accessed to identify target caching agents for snoop messages. In order to reduce message traffic, snoop message are sent only to the identified targets.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Applicant: Arm Limited
    Inventors: Gurunath Ramagiri, Jamshed Jalal, Mark David Werkheiser, Tushar P. Ringe, Mukesh Patel, Sakshi Verma
  • Patent number: 11256646
    Abstract: An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: February 22, 2022
    Assignee: Arm Limited
    Inventors: Tushar P Ringe, Jamshed Jalal, Gurunath Ramagiri, Ashok Kumar Tummala, Mark David Werkheiser
  • Patent number: 11188377
    Abstract: Apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating the interconnects are disclosed. A master apparatus can issue an individual all-zero-data write transaction specifying a data storage location to the interconnect, which conveys the individual all-zero-data write transaction to a target device which writes all-zero-data at the data storage location. No write data is conveyed with the individual all-zero-data write transaction, so that the individual all-zero-data write transaction may be used to clear the data storage location without adding to congestion of a write data channel in the interconnect.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Mark David Werkheiser, Phanindra Kumar Mannava, Bruce James Mathewson
  • Patent number: 11086802
    Abstract: A technique is provided for routing access requests within an interconnect. An apparatus provides a plurality of requester elements for issuing access requests, and a slave element to be accessed in response to the access requests. An interconnect is used to couple the plurality of requester elements with the slave element, and provides an intermediate element that acts as a point of serialisation to order the access requests issued by the plurality of requester elements via the intermediate element. Communication channels are provided within the interconnect to support communication between each of the requester elements and the intermediate element, and between the intermediate element and the slave element.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 10, 2021
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Tushar P. Ringe, Mark David Werkheiser, Gurunath Ramagiri
  • Publication number: 20210216241
    Abstract: A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.
    Type: Application
    Filed: January 15, 2020
    Publication date: July 15, 2021
    Inventors: Gurunath RAMAGIRI, Jamshed JALAL, Mark David WERKHEISER, Tushar P. RINGE, Klas Magnus BRUCE, Ritukar KHANNA
  • Publication number: 20210149833
    Abstract: An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order.
    Type: Application
    Filed: November 15, 2019
    Publication date: May 20, 2021
    Inventors: Tushar P. RINGE, Jamshed JALAL, Gurunath RAMAGIRI, Ashok Kumar TUMMALA, Mark David WERKHEISER
  • Publication number: 20210103460
    Abstract: Apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating the interconnects are disclosed. A master apparatus can issue an individual all-zero-data write transaction specifying a data storage location to the interconnect, which conveys the individual all-zero-data write transaction to a target device which writes all-zero-data at the data storage location. No write data is conveyed with the individual all-zero-data write transaction, so that the individual all-zero-data write transaction may be used to clear the data storage location without adding to congestion of a write data channel in the interconnect.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Inventors: Jamshed JALAL, Mark David WERKHEISER, Phanindra Kumar MANNAVA, Bruce James MATHEWSON
  • Patent number: 10877904
    Abstract: A system, apparatus and method for protecting coherent memory contents in a coherent data processing network by filtering data access requests and snoop response based on the Read/Write (R/W) access permissions. Requests are augmented with access permissions in memory protection units and the access permissions are used to control memory access by home nodes of the network.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: December 29, 2020
    Assignee: Arm Limited
    Inventors: Gurunath Ramagiri, Tushar P. Ringe, Mukesh Patel, Jamshed Jalal, Ashok Kumar Tummala, Mark David Werkheiser
  • Patent number: 10802534
    Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 13, 2020
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Ramamoorthy Guru Prasadh, Amaresh Pangal, Kishore Kumar Jagadeesha, Mark David Werkheiser
  • Publication number: 20200301854
    Abstract: A system, apparatus and method for protecting coherent memory contents in a coherent data processing network by filtering data access requests and snoop response based on the Read/Write (R/W) access permissions. Requests are augmented with access permissions in memory protection units and the access permissions are used to control memory access by home nodes of the network.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Applicant: Arm Limited
    Inventors: Gurunath Ramagiri, Tushar P. Ringe, Mukesh Patel, Jamshed Jalal, Ashok Kumar Tummala, Mark David Werkheiser
  • Patent number: 10761987
    Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Mark David Werkheiser, Michael Filippo, Klas Magnus Bruce, Paul Gilbert Meyer
  • Publication number: 20200257647
    Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 13, 2020
    Inventors: Tushar P. Ringe, Jamshed Jalal, Anitha Kona, Mark David Werkheiser
  • Publication number: 20200241589
    Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.
    Type: Application
    Filed: January 24, 2019
    Publication date: July 30, 2020
    Inventors: Tushar P. Ringe, Ramamoorthy Guru Prasadh, Amaresh Pangal, Kishore Kumar Jagadeesha, Mark David Werkheiser
  • Patent number: 10725958
    Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 28, 2020
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Jamshed Jalal, Anitha Kona, Mark David Werkheiser
  • Patent number: 10698825
    Abstract: In a system-on-chip there is a local interconnect to connect local devices on the chip to one another, a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect, and a cache-coherent device. The cache-coherent device has a cache-coherency look-up table having entries for shared cache data lines. When a data access request is received via the inter-chip interconnect and the local interconnect a system-unique identifier for a request source of the data access request is generated in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip. The bit-set used to express the system-unique identifier is larger than the bit-set used to express the inter-chip request source identifier.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: June 30, 2020
    Assignee: Arm Limited
    Inventors: Gurunath Ramagiri, Ashok Kumar Tummala, Mark David Werkheiser, Jamshed Jalal, Premkishore Shivakumar, Paul Gilbert Meyer
  • Publication number: 20200167284
    Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Jamshed JALAL, Mark David WERKHEISER, Michael FILIPPO, Klas Magnus BRUCE, Paul Gilbert MEYER
  • Patent number: 10657055
    Abstract: An apparatus and method are provided for managing snoop operations. The apparatus has an interface for receiving access requests from any of N master devices that have associated cache storage, each access request specifying a memory address within memory associated with the apparatus. Snoop filter storage is provided that has a plurality of snoop filter entries, where each snoop filter entry identifies a memory portion and snoop control information indicative of the master devices that have accessed that memory portion. When an access request received at the interface specifies a memory address that is within the memory portion associated with a snoop filter entry, snoop control circuitry uses the snoop control information in that snoop filter entry to determine which master devices to subject to a snoop operation.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 19, 2020
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Mark David Werkheiser, Gurunath Ramagiri, Mukesh Patel
  • Patent number: 10591977
    Abstract: A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 17, 2020
    Assignee: Arm Limited
    Inventors: Mark David Werkheiser, Dominic William Brown, Ashley John Crawford, Paul Gilbert Meyer
  • Patent number: 10585449
    Abstract: Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: March 10, 2020
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Ramamoorthy Guru Prasadh, Amaresh Pangal, Kishore Kumar Jagadeesha, Mark David Werkheiser
  • Patent number: 10489315
    Abstract: A method and apparatus for controlling direct memory transfer (DMT) in a data processing system with mismatched bus-widths in which a home node automatically determines, from a read request received from a requestor node, whether DMT should be enabled or disabled dependent on the bus-widths of the requestor node and a target slave node and on the size of the access. Optionally, when the slave node has a smaller bus width than the requestor node, a data combiner at an upload port for the target slave node merges two or more data beats of requested data received from the target slave node to form a single wider beat and transmits the single wider beat to the requestor node. A counter may be used to determine when a data buffer in the data combiner has sufficient space to store data beats to be merged.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: November 26, 2019
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Jamshed Jalal, Phanindra Kumar Mannava, Mark David Werkheiser, Ramamoorthy Guru Prasadh, Gurunath Ramagiri