Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units.

Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

Abstract: In a system-on-chip there is a local interconnect to connect local devices on the chip to one another, a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect, and a cache-coherent device. The cache-coherent device has a cache-coherency look-up table having entries for shared cache data lines. When a data access request is received via the inter-chip interconnect and the local interconnect a system-unique identifier for a request source of the data access request is generated in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip. The bit-set used to express the system-unique identifier is larger than the bit-set used to express the inter-chip request source identifier.

Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units.

Abstract: An apparatus and method are provided for managing snoop operations. The apparatus has an interface for receiving access requests from any of N master devices that have associated cache storage, each access request specifying a memory address within memory associated with the apparatus. Snoop filter storage is provided that has a plurality of snoop filter entries, where each snoop filter entry identifies a memory portion and snoop control information indicative of the master devices that have accessed that memory portion. When an access request received at the interface specifies a memory address that is within the memory portion associated with a snoop filter entry, snoop control circuitry uses the snoop control information in that snoop filter entry to determine which master devices to subject to a snoop operation.

Abstract: A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.

Abstract: Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.

Abstract: A method and apparatus for controlling direct memory transfer (DMT) in a data processing system with mismatched bus-widths in which a home node automatically determines, from a read request received from a requestor node, whether DMT should be enabled or disabled dependent on the bus-widths of the requestor node and a target slave node and on the size of the access. Optionally, when the slave node has a smaller bus width than the requestor node, a data combiner at an upload port for the target slave node merges two or more data beats of requested data received from the target slave node to form a single wider beat and transmits the single wider beat to the requestor node. A counter may be used to determine when a data buffer in the data combiner has sufficient space to store data beats to be merged.

Abstract: A system, apparatus and method for ordering a sequence of processing transactions for a plurality of peripheral units. The sequence of transactions is accomplished by mapping an incoming address to a target endpoint. The ordering of the transactions is agnostic to the type of endpoint being targeted and only considers an identifier of the transaction for ordering purposes.

Abstract: A data processing system, having two or more of processors that access a shared data resource, and method of operation thereof. Data stored in a local cache is marked as being in a ‘UniqueDirty’, ‘SharedDirty’, ‘UniqueClean’, ‘SharedClean’ or ‘Invalid’ state. A snoop filter monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. The snoop filter cache does not identify any local cache that stores the block of data in a ‘SharedDirty’ state, resulting in a smaller snoop filter cache size and simple snoop control logic. The data processing system by be defined by instructions of a Hardware Description Language.

Abstract: A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. This enables greater efficiency in cache usage since data which the requesting master considers is unlikely to be needed again can be invalidated from caches located outside the master device itself.

Abstract: A data processing system, having two or more of processors that access a shared data resource, and method of operation thereof. Data stored in a local cache is marked as being in a ‘UniqueDirty’, ‘SharedDirty’, ‘UniqueClean’, ‘SharedClean’ or ‘Invalid’ state. A snoop filter monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. The snoop filter cache does not identify any local cache that stores the block of data in a ‘SharedDirty’ state, resulting in a smaller snoop filter cache size and simple snoop control logic. The data processing system by be defined by instructions of a Hardware Description Language.

Abstract: A method and apparatus for controlling direct memory transfer (DMT) in a data processing system with mismatched bus-widths in which a home node automatically determines, from a read request received from a requestor node, whether DMT should be enabled or disabled dependent on the bus-widths of the requestor node and a target slave node and on the size of the access. Optionally, when the slave node has a smaller bus width than the requestor node, a data combiner at an upload port for the target slave node merges two or more data beats of requested data received from the target slave node to form a single wider beat and transmits the single wider beat to the requestor node. A counter may be used to determine when a data buffer in the data combiner has sufficient space to store data beats to be merged.

Abstract: A data processing system, having two or more of processors that access a shared data resource, and method of operation thereof. Data stored in a local cache is marked as being in a ‘UniqueDirty’, ‘SharedDirty’, ‘UniqueClean’, ‘SharedClean’ or ‘Invalid’ state. A snoop filter monitors access by the processors to the shared data resource, and includes snoop filter control logic and a snoop filter cache configured to maintain cache coherency. The snoop filter cache does not identify any local cache that stores the block of data in a ‘SharedDirty’ state, resulting in a smaller snoop filter cache size and simple snoop control logic. The data processing system by be defined by instructions of a Hardware Description Language.

Abstract: A system comprises a number of master devices and an interconnect for managing coherency between the master devices. In response to a read-with-overridable-invalidate transaction received by the interconnect from a requesting master device requesting that target data associated with a target address is provided to the requesting master device, when target data associated with the target address is stored by a cache, the interconnect issues a snoop request to said cache triggering invalidation of the target data from the cache except when the interconnect or cache determines to override the invalidation and retain the target data in the cache. This enables greater efficiency in cache usage since data which the requesting master considers is unlikely to be needed again can be invalidated from caches located outside the master device itself.

Abstract: A data processing system includes a snoop filter organized as a number of lines, each storing an address tag associated with the address of data stored in one or more caches of the system, a coherency state of the data, and presence data. A snoop controller sends snoop messages in response to data access requests. The presence data is configurable in a first format, in which the value of a bit in the presence data is indicative of a subset of the nodes for which at least one node in the subset has a copy of the data in its local cache, and in a second format, in which the presence data comprises a unique identifier of a node having a copy of the data in its local cache. The snoop controller sends snoop messages to the nodes indicated by the presence data.

Abstract: A data processing system includes a snoop filter organized as a number of lines, each storing an address tag associated with the address of data stored in one or more caches of the system, a coherency state of the data, and presence data. A snoop controller sends snoop messages in response to data access requests. The presence data is configurable in a first format, in which the value of a bit in the presence data is indicative of a subset of the nodes for which at least one node in the subset has a copy of the data in its local cache, and in a second format, in which the presence data comprises a unique identifier of a node having a copy of the data in its local cache. The snoop controller sends snoop messages to the nodes indicated by the presence data.

Abstract: A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.