Abstract: An apparatus for planarizing semiconductor wafers in its preferred form includes a rotatable platen for polishing a surface of the semiconductor wafer and a motor for rotating the platen. A non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. A polishing head holds the surface of the semiconductor wafer in juxtaposition relative to the non-circular pad. A polishing head displacement mechanism moves the polishing head and semiconductor wafer across and past a peripheral edge of the non-circular pad to effectuate a uniform polish of the semiconductor wafer surface. Also disclosed is a method for planarizing a semiconductor surface using a non-circular polishing pad.

Abstract: The present invention develops a bond pad interconnect in an integrated circuit device, by forming an aluminum pad; bonding a metal layer (such as copper (Cu), nickel (Ni), tungsten (W), gold (Au), silver (Ag) or platinum (Pt)) or a metal alloy (such as titanium nitride) to the aluminum bond pad by chemical vapor deposition or by electroless deposition; and adhering a conductive epoxy film to the metal layer, thereby forming a low resistive bond pad interconnect.

Abstract: A polishing pad is provided, having its face shaped to produce controlled nonuniform removal of material from a workpiece. Non-uniformity is produced as a function of distance from the pad's rotational axis (the working radius). The pad face is configured with both raised, contact regions and voided, non-contact regions such that arcuate abrasive contact varies nonuniformly as a function of distance from the pad's rotational axis. Void density at any distance may be produced by several techniques such as varying void size as a function of working radius or varying the number of voids per unit area as a function of working radius. Either technique produces variation in voided area per total unit area for rings of pad surface concentric with the rotational axis having infintesimally small width.

Abstract: Highly conformal layers of either titanium, Ti, titanium nitride, TiN, or titanium oxide, TiO.sub.x, are formed on exposed surfaces of silicon substrates by first forming a very thin chemical vapor deposition (CVD) layer of either doped polysilicon or a chosen metallic silicide, such as titanium silicide, tungsten silicide, tantalum silicide, or molybdenum silicide on the exposed silicon surfaces and any masking material remaining thereon. Thereafter, the layered structure is transferred to an electroplating bath wherein a layer of titanium is plated on the surfaces of the metallic silicide film using either an aqueous electroplating solution, a non-aqueous solution or a molten salt solution. Then, the structure is transferred to either an anneal furnace or to a rapid thermal processor (RTP) and heated to a predetermined elevated temperature for a predetermined time in the presence of nitrogen, using either nitrogen gas, N.sub.2, or ammonia, NH.sub.

Abstract: A method of increasing capacitance by surface roughening in semiconductor wafer processing includes the following steps: a) applying a first layer of material atop a substrate thereby defining an exposed surface; b) incontinuously adhering discrete solid particles to the first layer exposed surface to roughen the exposed surface; and c) applying a second layer of material atop the first layer and adhered solid particles to define an outer surface, the particles adhered to the first layer inducing roughness into the outer surface thereby increasing its surface area and accordingly capacitance of the second layer in the final wafer structure.

Abstract: An apparatus for planarizing semiconductor wafers in its preferred form includes a rotatable platen for polishing a surface of the semiconductor wafer and a motor for rotating the platen. A non-circular pad is mounted atop the platen to engage and polish the surface of the semiconductor wafer. A polishing head holds the surface of the semiconductor wafer in juxtaposition relative to the non-circular pad. A polishing head displacement mechanism moves the polishing head and semiconductor wafer across and past a peripheral edge of the non-circular pad to effectuate a uniform polish of the semiconductor wafer surface. Also disclosed is a method for planarizing a semiconductor surface using a non-circular polishing pad.

Abstract: A method and apparatus for improving planarity of chemical mechanical planarization of semiconductor wafers. The wafer is affixed to the planar surface of a wafer carrier. A planar platen, on which is mounted a polishing pad, is moved about in a plane parallel to the pad surface with either an orbital, fixed-direction vibratory, or random-direction vibratory motion. In one embodiment of the invention, pressure between the surface of the wafer to be polished and the moving polishing pad is generated by the force of gravity acting on at least the wafer and the carrier; in another it is provided by a mechanical force applied normal to the wafer surface. The polishing pad is wetted with a slurry having abrasive particles suspended in a liquid which may be chemically reactive with respect to at least one material on the wafer.

Abstract: A method of forming a capacitor in semiconductor water processing comprising the following steps: a) providing a conductively doped first layer of polysilicon atop a silicon wafer to a first thickness; b) depositing an undoped second layer of polysilicon over the conductively doped first layer of polysilicon to a second thickness, the layer of undoped polysilicon being deposited at a deposition temperature of at least 590.degree. and having an upper surface; c) impinging laser energy onto the upper surface of the second polysilicon layer at a laser fluence of 0.3 J/cm.sup.2 or greater to roughen the upper surface and thereby increase the capacitance of the second polysilicon layer; d) patterning and etching the first and second polysilicon layers to define a lower capacitor plate; e) providing a layer of capacitor dielectric atop the roughened second polysilicon layer upper surface; and f) providing a layer of conductive material atop the capacitor dielectric to define an upper capacitor plate.

Abstract: A polishing pad for semiconductor wafers, having a face shaped to provide a constant, or nearly constant, surface contact rate to a workpiece such as a semiconductor wafer, in order to effect improved planarity of the workpiece. The favored face shape is a sunburst pattern having nontapered rays, coaxial with the pad's rotation.

Abstract: A masked, conformal electrodeposition process for copper metallization of integrated circuits. The process is considerably less complex than other metallization processes utilizing electrodeposition, and provides excellent step coverage for sub-micron contact openings. Full-step coverage has been obtained with the process for contact openings as small as 0.5 microns in diameter. The process begins with the blanket sputter or LPCVD deposition of a thin conductive barrier layer of a material such as titanium nitride, titanium-tungsten or nitrided titanium-tungsten. A photoresist reverse image of the maskwork that normally would be used to etch the metallization pattern on the circuitry is created on the wafer on top of the barrier layer. As an option, the reverse image of the desired metallization pattern may be created by etching a dielectric material layer such as silicon dioxide or silicon nitride, using a photoresist reverse image as a template.

Abstract: An improved DRAM cell having a tantalum metal lower plate, a tantalum-silicide buried contact, and a tantalum oxide capacitor dielectric layer is disclosed. Also disclosed are several methods for fabricating the improved cell. Fabrication of an array of the improved cells proceeds through the storage-node contact opening stage in a manner consistent with the fabrication process utilized for conventional stacked-cell DRAM arrays. The process for fabricating the improved cells deviates from convention after storage-node contact openings are formed. A tantalum metal layer is conformally deposited over the wafer surface, patterned and etched to create individual storage-node plates. The wafer is then subjected to an elevated temperature step in an oxygen ambient, which creates both a tantalum silicide layer at the tantalum-silicon interface of each storage-node contact, and a tantalum oxide dielectric layer on the exposed surfaces of each storage-node plate.

Abstract: The invention is a method of forming a conductive contact plug and an interconnect line independent of each other. The contact plug is formed using laser planarization and a blanket etch back. The invention is also the contact plug thus formed. The contact plug and interconnect line may be fabricated with conductive materials having substantially similar methods of deposition. The integrity of the contact plug is enhanced using laser planarization.The process begins with a wafer having a dielectric layer, the upper surface of which has been planarized. A masking step defines a contact hole. An etch creates the contact hole which passes through the dielectric layer to a conductive region where contact is to be made. A first layer of conductive material is then deposited overlying the dielectric layer. A layer of material having an anti-reflective coating (ARC) (or a layer of material having a higher boiling point than the first layer) is deposited overlying the first layer.

Abstract: A process for texturization of polycrystalline silicon comprising the steps of utilizing gas phase nucleation by injecting a material to a cause heterogeneous nucleation or by increasing deposition temperature or pressure to cause a homogeneous nucleation of the silicon source itself. Heterogeneous or homogeneous gas phase nucleation causes large, stable textures in the deposited polysilicon that can be doped using conventional fabrication techniques.

Abstract: A process for texturization of polycrystalline silicon comprising the steps of preparing the wafer surface prior to poly deposition with a material which will cause the poly to preferentially nucleate during deposition and form poly nodules on the wafer surface. Polysilicon will continue to coat the previously created poly nodules throughout poly deposition, thereby resulting in a stable, texturized polysilicon structure.

Abstract: A method of forming a conductive via plug or an interconnect line, or both, of solid ductile metal within an integrated circuit using plastic deformation of the solid metal, and a dry polishing method of removing excess metal from a metal layer atop an underlying layer on a semiconductor substrate wafer. The process begins with a wafer having a dielectric layer, the upper surface of which has been planarized. If both conductive via plugs and interconnect lines are both required within the circuit, a first masking step defines the interconnect lines. A first etch creates channels in the interconnect line locations. A second masking step defines the vias. A second etch creates the vias which pass through the dielectric layer to conductive regions below where contact is to be made. A layer of solid ductile metal is then deposited on top of the dielectric layer.

Abstract: A process for creating and removing temporary silicon dioxide structures on an in-process integrated circuit with minimal effect on existing permanent silicon dioxide structures that are exposed. The process comprises the steps of blanket depositing an ozone-TEOS silicon dioxide layer through chemical vapor deposition on top of the in-process integrated circuit, thus covering permanent structures formed from conventional silicon dioxides (e.g. TEOS and thermal oxides), etching the ozone-TEOS layer to create said temporary structures, and removing the temporary structures using dilute hydrofluoric acid.

Abstract: A polishing pad for semiconductor wafers, having a face shaped by a series of voids. The voids are substantially the same size, but the frequency of the voids increases with increasing radial distance to provide a constant, or nearly constant, surface contact rate to a workpiece such as a semiconductor wafer, in order to effect improved planarity of the workpiece.

Abstract: An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly) and incorporates self-aligned salicidation of conductive regions. The object of the improved process is to reduce the cost and improve the reliability, performance and manufacturability of CMOS devices by a process which features a dramatically reduced number of photomasking steps and which further allows self-aligned salicidation of transistor conductive regions. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete.

Abstract: Novel amine-based precursor compounds comprising the condensation products of dialkylenetriamine and alpha, beta-unsaturated acid halides are disclosed, as well as composite membranes containing such compounds, the membranes being useful in RO-type processes for desalination and the removal of low molecular weight organic compounds such as phenols and carboxylic acids.