Abstract: A data processing system includes a GPU and a switching instruction section. The GPU performs in a time-divided manner a process of generating a plurality of pieces of data corresponding to a plurality of applications executed in parallel. In the case where the GPU completes a process of generating one unit of data that is data corresponding to a first application and that is to be handed over to subsequent processing sections, the switching instruction section instructs the GPU to switch to a process of generating an image corresponding to a second application different from the first application.

Abstract: A graphics processing unit (GPU) includes one or more processor cores adapted to execute a software-implemented shader program, and one or more hardware-implemented ray tracing units (RTU) adapted to traverse an acceleration structure to calculate intersections of rays with bounding volumes and graphics primitives asynchronously with shader operation. The RTU implements traversal logic to traverse the acceleration structure including transformation of rays as needed to account for variations in coordinate space between levels, stack management, and other tasks to relieve burden on the shader, communicating intersections to the shader which then calculates whether the intersection hit a transparent or opaque portion of the object intersected. Thus, one or more processing cores within the GPU perform accelerated ray tracing by offloading aspects of processing to the RTU, which traverses the acceleration structure within which the 3D environment is represented.

Abstract: A device and computer program product including one or more processors and a memory coupled to the one or more processors. The device being configured to selectively run in a timing testing mode or in a mode of operation other than the timing testing mode, wherein in the timing testing mode the device is configured to attempt to induce skew.

Abstract: A graphics processing unit (GPU) includes one or more processor cores adapted to execute a software-implemented shader program, and one or more hardware-implemented ray tracing units (RTU) adapted to traverse an acceleration structure to calculate intersections of rays with bounding volumes and graphics primitives asynchronously with shader operation. The RTU implements traversal logic to traverse the acceleration structure including transformation of rays as needed to account for variations in coordinate space between levels, stack management, and other tasks to relieve burden on the shader, communicating intersections to the shader which then calculates whether the intersection hit a transparent or opaque portion of the object intersected. Thus, one or more processing cores within the GPU perform accelerated ray tracing by offloading aspects of processing to the RTU, which traverses the acceleration structure within which the 3D environment is represented.

Abstract: Methods for graphics processing are provided. One example method includes executing a plurality of kernels using a plurality of graphics processing units (GPUs), wherein responsibility for executing a corresponding kernel is divided into one or more portions each of which being assigned to a corresponding GPU. The method includes generating a plurality of dependency data at a first kernel as each of a first plurality of portions of the first kernel completes processing. The method includes checking dependency data from one or more portions of the first kernel prior to execution of a portion of a second kernel. The method includes delaying execution of the portion of the second kernel as long as the corresponding dependency data of the first kernel has not been met.

Abstract: A device having a Graphics Processing Unit (GPU) may be configured to selectively run in a normal mode or a timing testing mode. In the timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU and test the application for errors in device hardware component and/or software component synchronization while the device is running in the timing testing mode.

Abstract: A new device executing an application on a new central processing unit (CPU), determines whether the application is for a legacy device having a legacy CPU. When the new device determines that the application is for the legacy device, it executes the application on the new CPU with selected available resources of the new device restricted to approximate or match a processing behavior of the legacy CPU, e.g., by reducing a usable portion of a return address stack of the new CPU and thereby reducing a number of calls and associated returns that can be tracked.

Abstract: To facilitate backwards compatibility, a computing device may respond to a call from an application for information regarding a processor on the computing device by returning information regarding a different processor than the processor on the computing device, including one or more of processor model, processor family, cache capabilities, translation lookaside buffer capabilities, processor serial number, processor brand, processor manufacturer, thread/core topology, cache topology, extended features, virtual address size, or physical address size that differs when the processor determines that the application is a legacy device application.

Abstract: An application designed for the current version of a system runs at a standard clock frequency of a current version of the system. Running the application at the standard clock frequency includes synchronizing operation of a processor of the current version of the system with the standard clock frequency. An application designed for a different version of the system characterized by a different standard clock frequency runs at a second clock frequency that is different than the standard clock frequency. Running the application at the second clock frequency includes synchronizing operation of the processor of the current version of the system with the second clock frequency.

Abstract: Methods for graphics processing are provided. One example method includes executing a plurality of kernels using a plurality of graphics processing units (GPUs), wherein responsibility for executing a corresponding kernel is divided into one or more portions each of which being assigned to a corresponding GPU. The method includes generating a plurality of dependency data at a first kernel as each of a first plurality of portions of the first kernel completes processing. The method includes checking dependency data from one or more portions of the first kernel prior to execution of a portion of a second kernel. The method includes delaying execution of the portion of the second kernel as long as the corresponding dependency data of the first kernel has not been met.

Abstract: Graphics processing renders a scene with a plurality of different rendering parameters for different locations on a screen area. Each primitive of a batch of primitives belonging to an object covering at least two of the zones of the screen area is assembled to a screen space. Assembling each of the primitives includes iterating each primitive with a primitive assembler for each of the zones covered by the object. Each said zone is associated with a different set of screen space transform parameters used to transform locations of vertices in the batch of primitives from a homogenous coordinate space to a screen space that is not flat. The zones are arranged to minimize an overlap between zones.

Abstract: A graphics processing unit (GPU) includes one or more processor cores adapted to execute a software-implemented shader program, and one or more hardware-implemented ray tracing units (RTU) adapted to traverse an acceleration structure to calculate intersections of rays with bounding volumes and graphics primitives. The RTU implements traversal logic to traverse the acceleration structure, stack management, and other tasks to relieve burden on the shader, communicating intersections to the shader which then calculates whether the intersection hit a transparent or opaque portion of the object intersected. Thus, one or more processing cores within the GPU perform accelerated ray tracing by offloading aspects of processing to the RTU, which traverses the acceleration structure within which the 3D environment is represented.

Abstract: A method, system and computer readable medium for running a legacy application on a non-legacy device. Operating parameters of the non-legacy device when running the legacy application are set based on one or more pre-determined heuristics for adjustment of operating parameters of the newer system when running the legacy application on the non-legacy device from one or more performance metrics and other performance information.

Abstract: A graphics processing unit (GPU) includes one or more processor cores adapted to execute a software-implemented shader program, and one or more hardware-implemented ray tracing units (RTU) adapted to traverse an acceleration structure to calculate intersections of rays with bounding volumes and graphics primitives asynchronously with shader operation. The RTU implements traversal logic to traverse the acceleration structure including transformation of rays as needed to account for variations in coordinate space between levels, stack management, and other tasks to relieve burden on the shader, communicating intersections to the shader which then calculates whether the intersection hit a transparent or opaque portion of the object intersected. Thus, one or more processing cores within the GPU perform accelerated ray tracing by offloading aspects of processing to the RTU, which traverses the acceleration structure within which the 3D environment is represented.

Abstract: Performance of a legacy application may be characterized for subsequent adjustment of operating parameters when running the legacy application on a newer system. The legacy application is run on an older system and one or more key performance metrics that must be met when the legacy application is run on the newer system are determined along with other performance information useful for later adjustment of operating parameters of the newer system when running the legacy application on the newer system.

Abstract: A new device executing an application on a new central processing unit (CPU), determines whether the application is for a legacy device having a legacy CPU. When the new device determines that the application is for the legacy device, it executes the application on the new CPU with selected available resources of the new device restricted to approximate or match a processing behavior of the legacy CPU, e.g.

Abstract: A data processing system includes a GPU and a switching instruction section. The GPU performs in a time-divided manner a process of generating a plurality of pieces of data corresponding to a plurality of applications executed in parallel. In the case where the GPU completes a process of generating one unit of data that is data corresponding to a first application and that is to be handed over to subsequent processing sections, the switching instruction section instructs the GPU to switch to a process of generating an image corresponding to a second application different from the first application.

Abstract: A new device executing an application on a new central processing unit (CPU), determines whether the application is for a legacy device having a legacy CPU. When the new device determines that the application is for the legacy device, it executes the application on the new CPU with selected available resources of the new device restricted to approximate or match a processing behavior of the legacy CPU.

Abstract: A method, system and non-transitory computer readable instructions for application patching comprising, concatenating compressed data or uncompressed data or a mixture of compressed and uncompressed data into a continuous data set into a continuous data set and dividing the continuous data set into variable sized data chunks. Compressing each of the variable sized data chunks and dividing each of the variable sized data chunks into fixed size data blocks. Encrypting the fixed size data blocks to generate encrypted fixed size data blocks and storing the encrypted fixed sized data blocks or sending the encrypted fixed size data blocks over a network.

Abstract: Methods for graphics processing are provided. One example method includes executing a plurality of kernels using a plurality of graphics processing units (GPUs), wherein responsibility for executing a corresponding kernel is divided into one or more portions each of which being assigned to a corresponding GPU. The method includes generating a plurality of dependency data at a first kernel as each of a first plurality of portions of the first kernel completes processing. The method includes checking dependency data from one or more portions of the first kernel prior to execution of a portion of a second kernel. The method includes delaying execution of the portion of the second kernel as long as the corresponding dependency data of the first kernel has not been met.