Abstract: A graphics processing unit (GPU) includes one or more processor cores adapted to execute a software-implemented shader program, and one or more hardware-implemented ray tracing units (RTU) adapted to traverse an acceleration structure to calculate intersections of rays with bounding volumes and graphics primitives. The RTU implements traversal logic to traverse the acceleration structure, stack management, and other tasks to relieve burden on the shader, communicating intersections to the shader which then calculates whether the intersection hit a transparent or opaque portion of the object intersected. Thus, one or more processing cores within the GPU perform accelerated ray tracing by offloading aspects of processing to the RTU, which traverses the acceleration structure within which the 3D environment is represented.

Abstract: A graphics processing unit (GPU) includes one or more processor cores adapted to execute a software-implemented shader program, and one or more hardware-implemented ray tracing units (RTU) adapted to traverse an acceleration structure to calculate intersections of rays with bounding volumes and graphics primitives asynchronously with shader operation. The RTU implements traversal logic to traverse the acceleration structure including transformation of rays as needed to account for variations in coordinate space between levels, stack management, and other tasks to relieve burden on the shader, communicating intersections to the shader which then calculates whether the intersection hit a transparent or opaque portion of the object intersected. Thus, one or more processing cores within the GPU perform accelerated ray tracing by offloading aspects of processing to the RTU, which traverses the acceleration structure within which the 3D environment is represented.

Abstract: In a computer graphics processing unit (GPU) having a texture unit, when pixel sample locations are based on a non-orthonormal grid in scene space, the texture unit receives texture space gradient values directly, e.g., from a shader unit or generates them from texture coordinates supplied, e.g., by a shader unit, and then applies a transformation to the gradient values configured to adjust the gradient values to those which would arise from the use of a orthonormal screen space grid.

Abstract: A graphics processing may include implementing a vertex shader and a pixel shader with a GPU. Vertex parameter values generated by the vertex shader may be stored in a memory. The pixel shader may access the vertex parameter values stored in the memory. Accessing the vertex parameter values may include disabling or bypassing hardware that performs interpolation on vertex parameter values. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: An application designed for the current version of a system runs at a standard clock frequency of a current version of the system. Running the application at the standard clock frequency includes synchronizing operation of a processor of the current version of the system with the standard clock frequency. An application designed for a different version of the system characterized by a different standard clock frequency runs at a second clock frequency that is different than the standard clock frequency. Running the application at the second clock frequency includes synchronizing operation of the processor of the current version of the system with the second clock frequency.

Abstract: To facilitate backwards compatibility, a computing device may respond to a call from an application for information regarding a processor on the computing device by returning information regarding a different processor than the processor on the computing device, including one or more of processor model, processor family, cache capabilities, translation lookaside buffer capabilities, processor serial number, processor brand, processor manufacturer, thread/core topology, cache topology, extended features, virtual address size, or physical address size that differs when the processor determines that the application is a legacy device application

Abstract: Methods for graphics processing are provided. One example method includes executing a plurality of kernels using a plurality of graphics processing units (GPUs), wherein responsibility for executing a corresponding kernel is divided into one or more portions each of which being assigned to a corresponding GPU. The method includes generating a plurality of dependency data at a first kernel as each of a first plurality of portions of the first kernel completes processing. The method includes checking dependency data from one or more portions of the first kernel prior to execution of a portion of a second kernel. The method includes delaying execution of the portion of the second kernel as long as the corresponding dependency data of the first kernel has not been met.

Abstract: A device having a Graphics Processing Unit (GPU) may be configured to selectively run in a normal mode or a timing testing mode. In the timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU and test the application for errors in device hardware component and/or software component synchronization while the device is running in the timing testing mode.

Abstract: An application runs at a first operating frequency if the application is designed for a current version of a system and runs at a second operating frequency if the application is designed for a prior version of the system that operates at a lower frequency than the first operating frequency. The second operating frequency may be higher than the operating frequency of the prior version of the system to account for differences in latency, throughput or other processing characteristics between the two systems. Software readable cycle counters are based on a spoof clock running at the operating frequency of the prior version of the system, rather than the true operating frequency. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: To facilitate backwards compatibility, a computing device may respond to a call from an application for information regarding a processor on the computing device by returning information regarding a different processor than the processor on the computing device.

Abstract: A device may be run in a timing testing mode in which the device is configured to disrupt timing of processing that takes place on the one or more processors while running an application with the one or more processors. The application may be tested for errors while the device is running in the timing testing mode.

Abstract: Graphics processing renders a scene with a plurality of different rendering parameters for different locations on a screen area. Each primitive of a batch of primitives belonging to an object covering at least two of the zones of the screen area is assembled to a screen space. Assembling each of the primitives includes iterating each primitive with a primitive assembler for each of the zones covered by the object. Each said zone is associated with a different set of screen space transform parameters used to transform locations of vertices in the batch of primitives from a homogenous coordinate space to a screen space that is not flat. The zones are arranged to minimize an overlap between zones.

Abstract: Performance of a legacy application may be characterized for subsequent adjustment of operating parameters when running the legacy application on a newer system. The legacy application is run on an older system and one or more key performance metrics that must be met when the legacy application is run on the newer system are determined along with other performance information useful for later adjustment of operating parameters of the newer system when running the legacy application on the newer system.

Abstract: Graphics processing renders a scene with a plurality of different rendering parameters for different locations on a screen area. Graphics depicting one or more objects mapped to a screen area are processed. The screen area includes a plurality of zones, each having a different set of rendering parameters. Primitives belonging to one of the objects that covers at least two of the zones are received. Each primitive is assembled to screen space by iterating each primitive over each zone it covers using the rendering parameters of the respective zone with each iteration.

Abstract: Performance of a legacy application may be characterized for subsequent adjustment of operating parameters when running the legacy application on a new system. The legacy application is run on the legacy system and one or more key performance metrics that must be met when the legacy application is run on the new system are determined along with other performance information useful for later adjustment of operating parameters of the new system when running the legacy application on the new system.

Abstract: A method, system and non-transitory instruction for reducing fragmentation in patch system with variable sized data chunks comprising, analyzing a data chunk fragmentation metric comparing data chunk fragmentation metric to a threshold and initiating data chunk coalescence when the fragmentation is exceeds a threshold.

Abstract: A method, system and non-transitory computer readable instructions for application patching comprising, concatenating uncompressed data into a continuous data set and dividing the continuous data set into variable sized data chunks. Compressing each of the variable sized data chunks and dividing each of the variable sized data chunks into fixed size data blocks. Encrypting the fixed size data blocks to generate encrypted fixed size data blocks and sending the encrypted fixed size data blocks over a network.

Abstract: A method, system and non-transitory computer readable instructions for update optimization comprising, receiving application metadata wherein the application metadata includes a likelihood of future data change metric for one or more regions of application data. Determining from the application metadata which regions of the application data have a high likelihood of data change and generating variable data chunk boundaries based on the regions of the application data that have the high likelihood of data change.

Abstract: In a computer graphics processing unit (GPU) having a texture unit, when pixel sample locations are based on a non-orthonormal grid in scene space, the texture unit receives texture space gradient values directly, e.g., from a shader unit or generates them from texture coordinates supplied, e.g., by a shader unit, and then applies a transformation to the gradient values configured to adjust the gradient values to those which would arise from the use of a orthonormal screen space grid.

Abstract: A graphics processing may include implementing a vertex shader and a pixel shader with a GPU. Vertex parameter values generated by the vertex shader may be stored in a memory. The pixel shader may access the vertex parameter values stored in the memory. Accessing the vertex parameter values may include disabling or bypassing hardware that performs interpolation on vertex parameter values. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.