Abstract: The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead.

Abstract: A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.

Abstract: Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existance of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.