Abstract: A graphics processing unit (GPU) of a processing system is partitioned into multiple dies (referred to as GPU chiplets) that are configurable to collectively function and interface with an application as a single GPU in a first mode and as multiple GPUs in a second mode. By dividing the GPU into multiple GPU chiplets, the processing system flexibly and cost-effectively configures an amount of active GPU physical resources based on an operating mode. In addition, a configurable number of GPU chiplets are assembled into a single GPU, such that multiple different GPUs having different numbers of GPU chiplets can be assembled using a small number of tape-outs and a multiple-die GPU can be constructed out of GPU chiplets that implement varying generations of technology.

Abstract: A cable shaving tool including a blade holder having a guide channel extending along the blade holder length. The guide channel includes a cable channel, and a control surface at opposing ends. A removable blade is secured to a blade support surface and the blade edge extends within the guide channel. The blade support and handle are disposed along a central axis. The shaving depth is determined by the differential between: (1) the distance from the cable channel to the bottom surface of the blade holder; and (2) the distance from the control surface to the bottom surface of the blade holder. The handle is secured to the blade holder and extends along the central axis, allowing an operator's hand to be positioned directly over the blade during a cut, apply a downward pressure on the cable to set the blade and then move the tool in a direction parallel to the cable length.

Abstract: Cascading execution of atomic operations, including: receiving a request for each thread of a plurality of threads to perform an atomic operation, wherein the plurality of threads comprises a plurality of thread subsets each corresponding to a local memory, wherein the local memory for a thread subset is accessible by the thread subset and inaccessible to a remainder of threads in the plurality of threads; generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset; and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.

Abstract: As part of rendering a scene including at least one graphics object in a display space, the display space is divided into a plurality of tiles. A determination is made that contents of at least two of the plurality of tiles are no longer used after a current render pass. A write back memory address associated with a second tile is changed to match a write back memory address associated with a first tile. As a result, data is overwritten on a same physical page.

Abstract: A processing system includes one or more accelerator units (AUs) each having a modular architecture. To this end, each AU includes a connection circuitry and one or more memory stacks disposed on the connection circuitry. Further, each AU includes one or more interposer dies each disposed on the connection circuitry such that each interposer die of the one or more interposer dies is communicatively coupled to a corresponding memory stack of the memory stacks via the connection circuitry. Further, each interposer die of each AU includes circuitry configured to concurrently support two or more types of compute dies.

Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.

Abstract: A processor for optimizing partial writes to compressed blocks is configured to identify that a write request targets less than an entirety of a compressed block of pixel data, identify, based on a compression key, a compressed segment of the compressed block of pixel data that includes a target of the write request, and decompress, responsive to the write request, only the identified compressed segment of the compressed block of pixel data.

Abstract: A cable-shaving tool for midspan shaving of a cable jacket includes a housing bottom having a first hinge member along an upper edge, a cavity, and a cable groove extending through a length of the housing bottom. The cable-shaving tool includes a second housing shell having an interior portion having a recess with an upper control surface, an exterior portion, and a second hinge member along a second housing shell edge engageable with the first hinge member. The second housing shell is rotatable about the first hinge member. The cable-shaving tool includes a blade removably securable between a blade holder and a blade support surface on the housing lid, the blade extending within a portion of the recess and a movable cable ramp disposed in the cavity of the bottom housing for urging the cable toward the blade when the second housing shell is in a closed position.

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

Abstract: A cable-shaving tool for midspan shaving of a cable jacket includes a housing bottom having a first hinge member along an upper edge, a cavity, and at least one cable groove extending through a length of the housing bottom. The cable-shaving tool includes a second housing shell having an interior portion having at least one recess having an upper control surface, an exterior portion, and a second hinge member along a second housing shell edge engageable with the first hinge member wherein the second housing shell is rotatable about the first hinge member. The cable-shaving tool includes a blade removably securable between a blade holder and a blade support surface on the housing lid, the blade extending within a portion of the recess and a movable cable ramp disposed in the cavity of the bottom housing for urging the cable toward the blade when the second housing shell is in a closed position.

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.

Abstract: A graphics processing unit (GPU) of a processing system is partitioned into multiple dies (referred to as GPU chiplets) that are configurable to collectively function and interface with an application as a single GPU in a first mode and as multiple GPUs in a second mode. By dividing the GPU into multiple GPU chiplets, the processing system flexibly and cost-effectively configures an amount of active GPU physical resources based on an operating mode. In addition, a configurable number of GPU chiplets are assembled into a single GPU, such that multiple different GPUs having different numbers of GPU chiplets can be assembled using a small number of tape-outs and a multiple-die GPU can be constructed out of GPU chiplets that implement varying generations of technology.

Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.

Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.

Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.

Abstract: Cascading execution of atomic operations, including: receiving a request for each thread of a plurality of threads to perform an atomic operation, wherein the plurality of threads comprises a plurality of thread subsets each corresponding to a local memory, wherein the local memory for a thread subset is accessible by the thread subset and inaccessible to a remainder of threads in the plurality of threads; generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset; and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.

Abstract: A processor for optimizing partial writes to compressed blocks is configured to identify that a write request targets less than an entirety of a compressed block of pixel data, identify, based on a compression key, a compressed segment of the compressed block of pixel data that includes a target of the write request, and decompress, responsive to the write request, only the identified compressed segment of the compressed block of pixel data.

Abstract: A processing unit performs a dispatch walk of a set of thread groups based on a programmable access pattern. The access pattern is stored at a table that is programmed with the access pattern based upon a specified command. By using the command to program the table with different access patterns, the dispatch order of the set of thread groups is adapted to better suit the processing of different data sets, thereby reducing power consumption at the processing unit, and improving overall processing efficiency.

Abstract: A processing system is configured to translate a first cache access pattern of a dispatch of work items to a cache access pattern that facilitates consumption of data stored at a cache of a parallel processing unit by a subsequent access before the data is evicted to a more remote level of the memory hierarchy. For consecutive cache accesses having read-after-read data locality, in some embodiments the processing system translates the first cache access pattern to a space-filling curve. In some embodiments, for consecutive accesses having read-after-write data locality, the processing system translates a first typewriter cache access pattern that proceeds in ascending order for a first access to a reverse typewriter cache access pattern that proceeds in descending order for a subsequent cache access. By translating the cache access pattern based on data locality, the processing system increases the hit rate of the cache.