Abstract: A process for separating a product web into discrete products is disclosed. The process can include transporting the product web in a machine direction, creating a line of weakness in the product web, and separating the product web into discrete product elements at the line of weakness.

Abstract: A system and method for integrating a plurality of subcircuit grids in a simulation environment. Upon obtaining a subcircuit layer of a particular granularity for each logical component of an electrical entity (e.g., a semiconductor die in a package and board environment), the nodes of a first subcircuit layer are interconnected to the nodes of a second subcircuit layer using a constraint-based search process.

Abstract: A method is provided for evaluating trace signal coupling in an electronic design (e.g., a package design). In the method, one or more trace signal coupling rules are formulated. One or more trace pairs designed to carry differential signals are then processed to determine whether the inter-trace spacing between the trace pairs violates the trace signal coupling rules. An indicator (e.g., a DRC and/or a report) is generated to identify violated trace signal coupling rules. Processing of the electronic design may be scoped according one or a group of signal nets, or one or a group of levels of the package design.

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract: An optical link adjacency discovery protocol is provided. The protocol includes a simple format that includes an identifier field of a local node and facility and an identifier field of an echo node and facility. An announce message, including a source field having an identifier of the local node written therein, is transmitted from the local node that terminates the created link to the far end node that terminates the other end of the optical link. The far end node receiving the announce message then generates an echo message including a source field and an echo field, the source field having an identifier of the second node and resources thereof associated with the link. The echo field of the echo message includes an identifier of the local node and resources thereof associated with the link. An optical network for implementing the optical link adjacency discovery protocol is also provided.

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract: A method for routing vias in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with an internal bond surface having a plurality of internal bond pads and an external bond surface with a plurality of external bond pads. A plurality of power vias and ground vias may be routed from a first redistribution layer between the internal bond surface and the external bond surface to a second redistribution layer between the first redistribution layer and the external bond surface based on a via pattern. The via pattern may comprise routing a power via and a ground via adjacent one another spaced apart at a distance that is substantially equal to a minimum routing pitch associated with the multilayer substrate.

Abstract: A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surface of the multilayer substrate, jogging a first differential signal line associated with a differential signal line pair at a first redistribution layer in a direction along the common plane, and jogging a second differential signal line associated with the differential signal line pair at a second redistribution layer along the common plane in a same direction as the first differential signal line to provide a substantially balanced differential signal line pair.

Abstract: Methods are provided for the analysis of gene expression utilizing RNA from hair follicles. Methods are also provided for evaluation of the biological activity of a candidate substance, genetic diagnosis, and evaluation of disease, each involving analysis of gene expression utilizing RNA from hair follicles.

Abstract: Systems and methods associated with generating node level bypass capacitor models are disclosed. One embodiment of a system may comprise a plurality of bypass capacitor circuit models associated with respective bypass capacitors and a node level model generator. The node level model generator may associate bypass capacitor information for a plurality of bypass capacitors from a data base associated with a multi-layer structure design with respective bypass capacitor circuit models to provide a node level capacitor model for the plurality of bypass capacitors.

Abstract: Various embodiments of a system, apparatus and method for determining the signal coupling coefficient of a path in the design of a substrate are disclosed. One apparatus embodiment comprises a path signal coupling coefficient tool.

Abstract: Various embodiments of a system, apparatus and method for determining the signal coupling coefficient of a line in the design of a substrate are disclosed. One apparatus embodiment comprises a line signal coupling coefficient tool.

Abstract: Various embodiments of a system, apparatus and method for determining the signal coupling coefficient of a via in the design of a substrate are disclosed. One apparatus embodiment comprises a via signal coupling coefficient tool.

Abstract: A method for verifying coupling in a differential via pair group includes identifying a differential via pair group in a design database and identifying a victim differential via pair in the differential via pair group. All other differential via pairs in the differential via pair group are identified as culprit differential pairs. The differential via pair group includes at least one culprit differential via pair. The method also includes obtaining a total coupling threshold level and calculating a total coupling factor for the victim differential via pair within the differential via pair group. The method also includes flagging the victim differential via pair if the calculated total coupling factor exceeds the total coupling threshold level.

Abstract: A method for verifying coupling in a differential trace pair group includes reading victim properties of a victim differential trace pair and culprit properties of a plurality of culprit differential trace pairs from a circuit design database. The method also includes calculating a plurality of coupling factors based on the victim properties and the culprit properties, one from each of the plurality of culprit differential trace pairs to the victim differential trace pair. The method also includes calculating a total coupling factor for the victim differential trace pair based on the plurality of coupling factors, and flagging the victim differential trace pair if the total coupling factor exceeds a total coupling threshold level.

Abstract: A method for calculating worst case coupling for a differential pair group includes identifying a victim differential pair and at least one culprit differential pair in the differential pair group, calculating a coupling factor between each of the culprit differential pairs and the victim differential pair, and summing the absolute value of each of the coupling factors to generate a worst case coupling factor.

Abstract: A method evaluates signal trace discontinuities in an electronic design of the type having one or more traces. The method includes the steps of formulating one or more trace discontinuity rules, processing the electronic design to determine whether the traces violate the trace discontinuity rules, and generating an indicator (e.g., a DRC) associated with the electronic design to identify violated trace discontinuity rules. Each level, each signal net, or a group of signal nets may be evaluated, for example, to ensure compliance with the trace discontinuity rules.

Abstract: According to at least one embodiment, a system comprises logic for maintaining homogeneity between a model of an object designed in a computer-aided modeling system and corresponding parameter information for the model included in a model documentation file.

Abstract: An absorbent garment has an absorbent assembly disposed within a garment shell configured for encircling a wearer's waist. The absorbent assembly has an inner surface adapted for contiguous relationship with the wearer's body, a front waist region in opposed relationship with a front waist region of the garment shell, a back waist region in opposed relationship with a back waist region of the garment shell, and a crotch region extending longitudinally between and interconnecting the front and back waist regions of the absorbent assembly. The absorbent assembly is releasably attached generally at a front waist end thereof to the garment shell generally at the front waist end of the garment shell, and is also releasably attached generally at a back waist end thereof to the garment shell generally at the back waist end of the garment shell.

Abstract: An absorbent garment has an absorbent assembly disposed within a garment shell configured for encircling the wearer's waist. The garment shell comprises a front panel assembly having laterally opposite side margins, and a back panel assembly having laterally opposite side margins. The absorbent assembly is attached at a front waist region thereof to the garment shell generally at the side margins of the front panel assembly to together define front side margins of the absorbent garment. The absorbent assembly is further attached at a back waist region thereof to the garment shell generally at the side margins of the back panel assembly to together define back side margins of the absorbent garment. The front side margins and the back side margins of the absorbent garment are releasably attached to each other to removably secure the absorbent garment on the wearer's waist.