Abstract: A method of genotyping includes applying a sample solution including a plurality of copies of a sample polynucleotide to an array of sensors. The sample polynucleotide includes a region associated with an allele. The method further includes measuring using a plurality of sensors of the array of sensors a characteristic of the region of the plurality of copies of the sample polynucleotide and determining using a computational circuitry and the measured characteristics a statistical value indicative of the allele.

Abstract: In an embodiment of the disclosure, there is provided a molybdenum composite hybrid laminate. The laminate has a plurality of composite material layers. The laminate further has a plurality of surface treated molybdenum foil layers interweaved between the composite material layers. The laminate further has a plurality of adhesive layers disposed between and bonding adjacent layers of the composite material layers and the molybdenum foil layers.

Abstract: One or more computer-readable storage media having computer-executable instructions embodied thereon are described. When executed, the computer-executable instructions cause at least one processor to define an analysis and an analysis data object related to a part, data for an analysis of the part at least partially available from a plurality of disparate applications related to the design, fabrication and testing of the part, verify that all the data needed for the analysis, as defined within the analysis data object, is available from at least one source of data, invoke an analysis of the part upon receipt of all of the data needed for the analysis, the analysis results populating the analysis data object, and storing the analysis data object such that the analysis results therein occur in a format unrelated to any of the applications that generated data used in the analysis.

Abstract: A semiconductor device comprises a substrate including isolation regions and active regions, and a high-k dielectric layer proximate the substrate. The high-k dielectric layer comprises a mixture formed by annealing at least one high-k material and at least one metal to oxidize the metal. The semiconductor device comprises a gate electrode proximate the high-k dielectric layer.

Abstract: A memory device comprises a substrate including isolation regions and active regions, and a floating gate stack proximate the substrate. The floating gate stack comprises a first high-k dielectric layer proximate the substrate, a first metal layer proximate the first high-k dielectric layer, and a second high-k dielectric layer proximate the first metal layer. The memory device comprises a control gate electrode proximate the floating gate stack.

Abstract: A semiconductor device comprises a substrate including isolation regions and active regions, and a high-k dielectric layer proximate the substrate. The high-k dielectric layer comprises a mixture formed by annealing at least one high-k material and at least one metal to oxidize the metal. The semiconductor device comprises a gate electrode proximate the high-k dielectric layer.

Abstract: Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide layer of less than 10 Angstroms, and annealing the reduced thickness oxide layer with ammonia. A semiconductor wafer comprises a silicon substrate, an oxide layer coupled to the silicon substrate where the oxide layer having a thickness of less than 10 Angstroms, and a high-k dielectric material deposited onto the oxide layer.

Abstract: A memory device comprises a substrate including isolation regions and active regions, and a floating gate stack proximate the substrate. The floating gate stack comprises a first high-k dielectric layer proximate the substrate, a first metal layer proximate the first high-k dielectric layer, and a second high-k dielectric layer proximate the first metal layer. The memory device comprises a control gate electrode proximate the floating gate stack.

Abstract: A semiconductor device comprises a substrate including isolation regions and active regions, a high-k material layer implanted with a species, the high-k material layer proximate the substrate, and a gate electrode proximate the high-k material layer.

Abstract: Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide layer of less than 10 Angstroms, and annealing the reduced thickness oxide layer with ammonia. A semiconductor wafer comprises a silicon substrate, an oxide layer coupled to the silicon substrate where the oxide layer having a thickness of less than 10 Angstroms, and a high-k dielectric material deposited onto the oxide layer.

Abstract: A method for forming a semiconductor device to produce graded doping in the source region and the drain region includes the steps of implanting the gate material, usually a polysilicon, with a dopant ion that varies the level of oxide formation on the gate. The dopant ion is driven into undoped polysilicon. Nitrogen ions, may also be implanted in the polysilicon to contain the previously implanted ions. For N-type transistors, typically arsenic is implanted. For P-type transistors, typically boron is implanted. Gates are formed. The gate structure is then oxidized. The oxidation process is controlled to grow a desired thickness of silicon dioxide on the gate. The portion of the gate carrying the dopant grows silicon dioxide either more quickly or more slowly. An isotropic etch can then used to remove a portion of the silicon oxide and form a knob on each sidewall of the gate.

Abstract: A dual level transistor and a fabrication technique. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed within a local trench etched into a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate and a first transistor formed on the global substrate. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric.

Abstract: A semiconductor device having a narrow gate electrode and a process of fabricating such a device is disclosed. The semiconductor device is formed by forming a polysilicon block over a substrate and forming a nitride spacer adjacent at least one sidewall of the polysilicon block. A portion of the polysilicon block opposite the nitride spacer is selectively removed. The polysilicon block is then oxidized to form an oxide portion adjacent one side of the polysilicon block and to form a narrow polysilicon block, wherein the nitride spacer inhibits oxidation of another side of the polysilicon block. The narrow polysilicon block is used as a gate electrode.