Abstract: Disclosed are methods and devices for providing improved semiconductor packages and POP IC assemblies using the improved packages with reduced warping. According to disclosed embodiments of the inventions, a packaged semiconductor device for use in a POP assembly includes an encapsulated region generally defined by the substrate surface. The encapsulant is provided with contact apertures permitting external communication with contacts on the substrate and coupled to an encapsulated chip. Preferred embodiments of the invention are described in which the contact aperture sidewalls are angled within the range of approximately 10-30 degrees or more from vertical and in which the contact aperture is provided a gas release channel to permit gas to escape during reflow.

Abstract: System and method for a thermal and space efficient integrated circuit package. A preferred embodiment comprises a first lead frame with a first surface to which a first die is attached and a second surface external to a multi-die package, a second lead frame with a first surface to which a second die is attached, wherein the first die and the second die are arranged so that they face each other. The present invention further comprises a first plurality of pins arranged around the first lead frame and a second plurality of pins arranged around the second lead frame. Finally, a package body encapsulates the first lead frame and the second lead frame with a portion of each pin in the first plurality of pins and the second plurality of pins extending outside the package body.

Abstract: According to one embodiment of the invention, a method of forming a system-in-a-package includes providing a first substrate, coupling a first die to a top surface of the first substrate, coupling one or more surface mount devices to a top surface of a second substrate, coupling the second substrate to a top surface of the first die, interconnecting the first substrate, the second substrate, and the first die, and encapsulating the first die, the second substrate and the surface mount devices.

Abstract: A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post.

Abstract: An electronic packaging combines features of a MAP (molded array package) and a lead frame package. The package includes an electrically conductive substrate somewhat like a lead frame package but defines a grid of conductive pads rather than a multiplicity of leads as is common with a lead frame package. An electronic chip is attached to the top surface of the lead frame, and the output terminals of the electronic chip are individually electrically connected to selected connecting pads of the lead frame grid array. Both flip chips and wire bond chips may be connected to the grid array. The channels defining the grid of connecting pads extend part way through the conductive substrate and increase in width from the top surface of the lead frame to the bottom of the channel such that the molding compound is locked in place when it cures and hardens.

Abstract: A BGA (Ball Grid Array Structure) having improved drop test performance by increasing the area of the solder bond at the corner of the array using existing assembling machinery.

Abstract: A system and method for changing a travel itinerary include receiving a request to make a change to a first travel itinerary that includes at least one segment, displaying an identification of one or more alternative segments, receiving a user selection of one of the alternative segments, modifying the first itinerary to include a reservation for the selected alternative segment, and releasing the segment of the first itinerary to be replaced by the selected alternative segments. The system and method may also include calculating a fare difference between the one or more alternative segments and the original segment to be replaced.

Abstract: A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post.

Abstract: A package device (10, 100) has one integrated circuit (22, 122) in a cavity (20, 120) in a package substrate (12, 122) and electrically coupled to one side (50, 150) of the package substrate. A second integrated circuit (32, 132) is mounted on another side of the package device and electrically coupled to that side as well. A third integrated circuit (38, 138) or more may be mounted on the second integrated circuit. Pads (16, 116, 116) useful for testing are present on both sides of the package substrate. The integrated circuits may be tested before final encapsulation to reduce the risk of providing completed packages with non-functional integrated circuits therein.

Abstract: A multi-die semiconductor package having an electrical interconnect frame. A top integrated circuit die is attached to the top side of an upper contact level of the frame and a bottom integrated circuit die is attached to the bottom side of the upper contact level of the frame. The die bond pads of the top die are electrically coupled (e.g. wired bonded) to pads of a lower contact level of the interconnect frame. The die bond pads of the bottom integrated circuit die are electrically coupled (e.g. wired bonded) to bond pads of the upper contact level of the frame. The bond pads of the lower contact level serve as external bond pads for the package. The frame may include inset structures, each having an upper portion located in the upper contact level and a lower portion located in the lower contact level.

Abstract: A packaged semiconductor device (20) has a first integrated circuit die (28) having a top surface with active electrical circuitry implemented thereon. The first die (28) is mounted in a cavity (21) of a first heat spreader (22). A second die (36) having electrical circuitry implemented on a top surface is attached to the top surface of the first die (28). Both of the die (28 and 36) are electrically connected to a substrate (24) mounted on the first heat spreader (22). A second heat spreader (40) is mounted on the top surface of the second die (36). The second heat spreader (40) provides an additional path for thermal dissipation of heat generated by the second die (36).

Abstract: A package substrate (12, 52) has a first surface, a second surface opposite a first surface, and a cavity (22, 70) formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die (20, 60) is placed in the cavity, and a conductive material (24, 72) is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer (28, 78) may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.

Abstract: A multi-die semiconductor package having an electrical interconnect frame. A top integrated circuit die is attached to the top side of an upper contact level of the frame and a bottom integrated circuit die is attached to the bottom side of the upper contact level of the frame. The die bond pads of the top die are electrically coupled (e.g. wired bonded) to pads of a lower contact level of the interconnect frame. The die bond pads of the bottom integrated circuit die are electrically coupled (e.g. wired bonded) to bond pads of the upper contact level of the frame. The bond pads of the lower contact level serve as external bond pads for the package. The frame may include inset structures, each having an upper portion located in the upper contact level and a lower portion located in the lower contact level.

Abstract: A package substrate (12, 52) has a first surface, a second surface opposite a first surface, and a cavity (22, 70) formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die (20, 60) is placed in the cavity, and a conductive material (24, 72) is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer (28, 78) may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.

Abstract: A packaged semiconductor device (20) has a first integrated circuit die (28) having a top surface with active electrical circuitry implemented thereon. The first die (28) is mounted in a cavity (21) of a first heat spreader (22). A second die (36) having electrical circuitry implemented on a top surface is attached to the top surface of the first die (28). Both of the die (28 and 36) are electrically connected to a substrate (24) mounted on the first heat spreader (22). A second heat spreader (40) is mounted on the top surface of the second die (36). The second heat spreader (40) provides an additional path for thermal dissipation of heat generated by the second die (36).

Abstract: A package device (10, 100) has one integrated circuit (22, 122) in a cavity (20, 120) in a package substrate (12. 122) and electrically coupled to one side (50, 150) of the package substrate. A second integrated circuit (32, 132) is mounted on another side of the package device and electrically coupled to that side as well. A third integrated circuit (38, 138) or more may be mounted on the second integrated circuit. Pads (16, 116, 116) useful for testing are present on both sides of the package substrate. The integrated circuits may be tested before final encapsulation to reduce the risk of providing completed packages with non-functional integrated circuits therein.

Abstract: A semiconductor device and its method of formation are disclosed wherein a first semiconductor substrate (20) and a second semiconductor substrate (21) are encapsulated in a no lead package (100). In some embodiments, a plurality of off die bond pads (30) is coupled to at least one of the first and second semiconductor substrates (20, 21). In some embodiments, the first semiconductor substrate (20) has a backside (40) which remains exposed after encapsulation.

Abstract: The replaceable power module includes a power section positioned between a cover and a frame. The cover is provided with clips to permit the attachment and detachment of the cover to the base as well the attachment and detachment of the power module to a surface mounted integrated circuit. The frame is provided with an opening for receiving the integrated circuit, and electrical contacts for electrically connecting the power module to the leads of an integrated circuit. The power section is electrically coupled to the frame and includes a battery and a crystal oscillator for controlling the integrated circuit.

Abstract: The power cap includes a power supply positioned between a cover and a base. The cover is provided with clips to permit the attachment and detachment of the cover to the power supply and the base. The base is provided with surface mounted NRTC or NVSRAM chips and electrical contacts. The power supply is provided with a crystal oscillator and a battery for controlling the operation of the NRTC or NVSRAM chips, and spring contacts for maintaining the electrical connection between the base and the power supply.

Abstract: The replaceable power module includes a power section positioned between a cover and a frame. The cover is provided with clips to permit the attachment and detachment of the cover to the base as well the attachment and detachment of the power module to a surface mounted integrated circuit. The frame is provided with an opening for receiving the integrated circuit, and electrical contacts for electrically connecting the power module to the leads of an integrated circuit. The power section is electrically coupled to the frame and includes a battery and a crystal oscillator for controlling the integrated circuit.