Abstract: Aspects of a method and system for a programmable interference suppression module may include receiving a communication signal comprising one or more desired signal, and one or more undesired signals. The communication signal may be utilized to generate estimated channel state information. The estimated channel state information may be formatted for use in interference suppression. A reduced interference signal may be generated from a delayed version of said communications signal and the estimated channel state information, wherein the one or more undesired signals may be attenuated. The reduced interference signal may be formatted for post-processing. The desired signals may comprise WCDMA and/or HSDPA signals, and the undesired signals may be inter-cell and/or intra-cell interference. Further processing may comprise HSDPA processing and/or RAKE finger processing. The communication signal may be a Universal Mobile Telecommunication System (UMTS) compliant signal.

Abstract: Aspects of a method and system for diversity processing utilizing a programmable interface suppression module may include one or more circuits that are operable to program an interference suppression module based on one or more interference cancellation parameters. A plurality of weighting factor values may be computed based on the one or more interference suppression parameters and a received plurality of multipath signals. A plurality of estimated signals may be generated based on the plurality of weighting factor values. A plurality of updated estimated signals may be generated based on the plurality of estimated signals. A plurality of interference suppressed signals may be generated based on the plurality of updated estimated signals.

Abstract: Multipath signals are processed to suppress interference utilizing a programmable interface suppression module. One or more circuits that are operable to retrieve at least a portion of stored data from a memory, wherein the stored data corresponds to signals received via a particular receiving antenna and assigned to a particular finger in a rake receiver. A plurality of weighting factor values may be computed based on one or more signals received via the particular receiving antenna. Estimated signals may be generated based on the portion of stored data and the plurality of weighting factors. Residual signals may be generated based on the portion of stored data and the estimated signals. The portion of stored data may be replaced in the memory with corresponding data generated utilizing the residual signals. A plurality of interference suppressed signals may be generated based on the plurality of residual signals.

Abstract: Aspects of a method and system for interference suppression between multipath signals utilizing a programmable interface suppression module may include one or more processors and/or circuits that are operable to program an interference suppression module based on one or more interference cancellation parameters. A plurality of weighting factor values may be determined based on the one or more interference suppression parameters and a received plurality of multipath signals. A plurality of estimated signals may be generated based on the plurality of weighting factor values. A plurality of updated estimated signals may be generated based on the plurality of estimated signals. A plurality of interference suppressed signals may be generated based on the plurality of updated estimated signals and/or a plurality of updated residual signals.

Abstract: Aspects of a method and system for interference suppression in WCDMA systems may include one or more circuits that are operable to receive a plurality of multipath signals via one or more receiving antennas. A plurality of weighting factor values may be computed based on the received multipath signals. Estimated signals may be based on the weighting factor values. Residual signals may be generated based on received signals and the estimated signals. Addback signals may be generated based on the estimated signals and the residual signals. Updated estimated signals may be generated based on the addback signals and the weighting factor values. Incremental signals may be generated based on the updated estimated signals and addback signals. Updated residual signals may be generated based on the incremental signals and previous residual signals. The interference suppressed signals may be generated based on the updated residual signals and updated estimated signals.

Abstract: A wireless system may receive a plurality of multipath signals from a plurality of transmitters and allocate per-cell modules for generating an interference suppressed signal from the multipath signals. Data symbols may be sequentially processed in the received multipath signals utilizing the per-cell modules and subtracting the processed symbols from a residual buffer storing the received multipath signals. Desired information received from one or more of the transmitters may be recovered utilizing the interference suppressed signal. Timing of the data symbols may be correlated utilizing a cell chip combiner. The data symbols may be descrambled utilizing conjugated scrambling codes associated with one of the plurality of transmitters. Orthogonal variable spreading factor (OVSF) codes may be generated utilizing a Walsh transform on the data symbols. Power levels of the OVSF codes may be estimated and estimated signals may be generated based on the OVSF codes and the estimated power levels.

Abstract: Aspects of a method and system for processing signals utilizing a programmable interference suppression module are provided. In this regard, a received signal may be iteratively processed to generate an interference suppressed representation of the received signal. The iterative processing may comprise a weighting iteration; an addback weighting and un-addback iteration, and an addback iteration. The weighting iteration may comprise generating one or more first estimate signals that estimate user signals present in the received signal. The addback, weighting, and un-addback iteration may comprise generating one or more incremental estimate signals based on the one or more first estimate signals and the one or more second estimate signals. The addback iteration may comprise generating an interference suppressed representation of the received signal based on at least the one or more second estimate signals.

Abstract: A wireless system may receive a plurality of multipath signals from a plurality of transmitters and sequentially process each of a plurality of data symbols in the received multipath signals utilizing a plurality of shared hardware modules within a chip. Desired information may be recovered from data transmitted by one or more of the transmitters utilizing the interference suppressed signal. Chips of data may be cell combined utilizing one or more of shared hardware modules. The shared modules may include channel rotation modules and sum and difference modules. One or more fast Hadamard transforms and/or inverse Hadamard transforms may be performed utilizing shared hardware modules. Data symbols may be interpolated, scrambled, descrambled, and/or weighted and added back utilizing the shared hardware modules.

Abstract: Aspects of a method and system for interference suppression using information from non-listened base stations are provided. In this regard, one or more circuits in a wireless communication device may be operable to receive a raw signal comprising one or more desired signals from one or more serving base transceiver stations (BTSs) and comprising one or more undesired signals from one or more non-listened BTSs. The one or more circuits may be operable to generate first estimate signals that estimate the one or more undesired signals as transmitted by the one or more non-listened BTSs, generate an interference suppressed version of the raw signal based on the first estimate signals, and recover the one or more desired signals from the interference suppressed version of the raw signal. The non-listened BTSs may comprise one or more BTSs that are not serving the wireless communication device and are not involved in a handoff of the wireless communication device.

Abstract: A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data.

Abstract: A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.

Abstract: A method for processing signals in a communication system is disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while storing on-chip, a portion of the plurality of information bits in the received HSDPA bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits in the received HSDPA bitstream may be partitioned into a functional data processing path and functional address processing path.

Abstract: Aspects of a method and system for processing audio signals via separate input and output processing paths are provided. In this regard, a hardware audio CODEC comprising one or more audio inputs and one or more audio outputs and may be enabled to route, via one or more switching elements, audio signals from any of the inputs to any of the outputs. The CODEC may be enabled to simultaneously process a plurality of audio signals based on a configuration of the switching elements. Upstream from the switching elements, received audio signals may be processed independent of an output to which the may be communicated. Downstream from said switching elements audio signals may be processed independent of an input via which the signals were received.

Abstract: Methods and systems for processing signals in a communication system are disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while simultaneously storing on-chip, a portion of the plurality of information bits in the received bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and the storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits may be partitioned into a functional data processing path and a functional address processing path.

Abstract: Certain aspects of a method and system for delay matching in a rake receiver are disclosed. Aspects of one method may include compensating for a delay associated with at least one or both of the following in a rake receiver: a control channel and a data channel, prior to individual processing of received data by the data channel and individual processing of received data by the control channel. The data channel or the dedicated physical channel (DPCH) may be delayed with respect to the control channel, which may comprise, for example, the common pilot control channel (CPICH), by a particular time period.

Abstract: Certain aspects of a method and system for hardware and software shareable DCT/IDCT control interface are provided. A single DCT/IDCT interface may be utilized to provide hardware or software control of a DCT/IDCT module. During hardware control the DCT/IDCT module may be utilized for JPEG compression, for example. During software control a CPU may utilize the DCT/IDCT module for audio, software, and/or video applications, for example. The interface may enable selecting a quantization table for use by the DCT/IDCT module. The interface may also enable selecting encoding or decoding operations to be performed by the DCT/IDCT module. The interface may also enable toggling between a first and a second portion of a data buffer utilized by the DCT/IDCT module. Moreover, the interface may enable starting processing of a data block by the DCT/IDCT module and indicating when the DCT/IDCT module has completed processing the data block.

Abstract: A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data.

Abstract: A method and system for programmable breakpoints in an integrated embedded image and video accelerator are described. Aspects of the system may include circuitry that enables generation of control signals for pipeline processing of video data within a single chip by at least selecting a target location of the video data and generating an interrupt at a time instant corresponding to the pipeline processing of the target location. The system may enable programmable breakpoints to be set and/or triggered based on policies determined in executable software. The ability to set programmable breakpoints may enable flexible utilization of system memory resources.

Abstract: Methods and systems for processing signals in a communication system are disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while simultaneously storing on-chip, a portion of the plurality of information bits in the received bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and the storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits may be partitioned into a functional data processing path and a functional address processing path.

Abstract: A baseband processing module includes an RX interface, a rake receiver combiner module, and may include additional components. The RX interface receives the baseband signals from an RF front end and creates baseband RX signal samples there from. The rake receiver combiner module includes control logic, an input buffer, a rake despreader module, and an output buffer. The rake despreader module is operable to despread the baseband RX signal samples in a time divided fashion to produce channel symbols including pilot channel symbols and physical channel symbols.