Abstract: A photonic integrated circuit (PIC) chip comprising an array of modulated sources, each providing a modulated signal output at a channel wavelength different from the channel wavelength of other modulated sources and a wavelength selective combiner having an input optically coupled to received all the signal outputs from the modulated sources and provide a combined output signal on an output waveguide from the chip. The modulated sources, combiner and output waveguide are all integrated on the same chip.

Abstract: A photonic integrated circuit (PIC) chip comprising an array of modulated sources, each providing a modulated signal output at a channel wavelength different from the channel wavelength of other modulated sources and a wavelength selective combiner having an input optically coupled to received all the signal outputs from the modulated sources and provide a combined output signal on an output waveguide from the chip. The modulated sources, combiner and output waveguide are all integrated on the same chip.

Abstract: A photonic integrated circuit (PIC) chip comprising an array of modulated sources, each providing a modulated signal output at a channel wavelength different from the channel wavelength of other modulated sources and a wavelength selective combiner having an input optically coupled to received all the signal outputs from the modulated sources and provide a combined output signal on an output waveguide from the chip. The modulated sources, combiner and output waveguide are all integrated on the same chip.

Abstract: Cleaved grooves, also referred to herein as “cleave streets”, are formed exclusively in a wafer passivation layer overlaying a wafer to provide for correctly aligned and sharp cleaves prior to singulation of the wafer into separate die or chips.

Abstract: An optical transport network comprises a monolithic transmitter photonic integrated circuit (TxPIC) InP-based chip and a monolithic receiver photonic integrated circuit (RxPIC) InP-based chip.

Abstract: A method is disclosed for optimizing optical channel signal demultiplexing in a monolithic receiver photonic integrated circuit (RxPIC) chip by providing an integrated channel signal demultiplexing with multiple waveguide input verniers provided to an WDM signal demultiplexer. The RxPIC chip may optionally include an integrated amplifier in at least some of the waveguide input verniers. The RxPIC chip may be comprised of, in monolithic form, a plurality of optional semiconductor optical amplifiers (SOAs) at the input of the chip to receive a WDM signal from an optical link which is provided along a plurality of waveguide input verniers to an integrated optical demultiplexer, such as, but not limited to, an arrayed waveguide grating (AWG), as a WDM signal demultiplexer. Thus, optical outputs from the respective semiconductor laser amplifiers are provided as vernier inputs to the optical demultiplexer forming a plurality of input verniers at the input to the optical demultiplexer.

Abstract: Disclosed is a method of in-wafer testing of integrated optical components and in-wafer chips with photonic integrated circuits (PICs).

Abstract: An optical-to-electrical-to-optical converter comprises a monolithic receiver photonic integrated circuit (RxPIC) InP-based chip comprising an optical waveguide formed in the chip from a chip input to receive a first multiplexed channel signal from an optical link and provide them to an arrayed waveguide grating (AWG) which demultiplexes the multiplexed channel signals and provides a plurality of electrical channel signals to an electronic regenerator. The regenerator regenerates the electrical channel signals to an original signal waveform and provides the reformed electrical signals to a monolithic transmitter photonic integrated circuit (TxPIC) InP-based chip having an array of modulated sources formed in the chip that are coupled as inputs to an arrayed waveguide grating (AWG). The TxPIC modulates the reformed electrical signals to form a plurality of optical channel sign which are combined to form a second first multiplexed channel signal for transmission on an optical link.

Abstract: Photonic integrated circuits (PICs), also referred to as opto-electronic integrated circuits (OEICs), and more particularly to a PIC in the form of an optical receiver PIC or RxPIC chip and an optical transmitter PIC (TxPIC) are employed in an optical transport network. Integrated on the RxPIC chip, starting at the input end which is coupled to receive multiplexed optical data signals from an optical transport network is an optical amplifier, an optical demultiplexer, and a plurality of on-chip photodiodes (PDs) each to receive a demultiplexed data signal from the AWG DEMUX for optical-to-electrical signal conversion. The optical input amplifier may be an on-chip gain clamped semiconductor optical amplifier (GC-SOA) or an off-chip fiber amplifier. The optical input amplifier may be optional if the channel signal demultiplexer provides for minimal insertion loss which is optimum with a properly designed arrayed waveguide grating (AWG) demultiplexer.

Abstract: Disclosed is a method of adjusting a center channel wavelength of a group of channel wavelengths from of a plurality of modulated sources, integrated in a photonic integrated circuit (PIC), relative to the center of a wavelength passband of an optical combiner, such as an arrayed waveguide array (AWG), also integrated in the photonic integrated circuit (PIC) and optically coupled to outputs from the modulated sources.

Abstract: An optical waveguide device, power coupler, a star coupler, a MMI coupler, an arrayed waveguide grating (AWG) or an Echelle grating, having at least one free space region with a plurality of optical waveguides coupled as inputs and separated by channels having a angled bottom portion, the channels monotonically decreasing in size or shape in a direction toward the free space region and optically coupling with adjacent waveguides at the interface region between the optical waveguides and the free space region so that insertion loss at the interface region is substantially reduced.

Abstract: A photonic integrated circuit (PIC) comprises a plurality of integrated optically coupled components formed in a surface of the PIC and a passivating layer overlies at least a portion of the PIC surface. The overlying passivating layer comprises a material selected from the group consisting of BCB, ZnS and ZnSe. Also, when the circuits are PIC chips are die in the semiconductor wafer, a plurality of linear cleave streets are formed in a wafer passivation layer where a pattern of the cleave streets define separate PIC chips in the wafer for their subsequent singulation from the wafer.

Abstract: An InP-based photonic integrated circuit (PIC) includes an optical passive element in the circuit with no bias current applied to such an element. A passivation cladding layer overlies a surface of the optical passive element where the passivation layer comprises benzocyclobutene polymer or BCB.

Abstract: A method for reducing insertion loss in a transition region between a plurality of input or output waveguides to a free space coupler region in a photonic integrated circuit (PIC) includes the steps of forming a passivation layer over the waveguides and region and forming the passivation overlayer such that it monotonically increases in thickness through the transition region to the free space coupler region.

Abstract: A monolithic photonic integrated circuit (PIC) chip comprises an array of modulated sources providing a plurality of channel signals of different wavelengths and an optical combiner coupled to receive the channel signals and produce a combined output of the channel signals. The arrays of modulated sources are formed as ridge waveguides to enhance the output power from the respective modulated sources so that the average output power from the sources is approximately 2 to 4 times higher than in the case of comparable arrays of modulated sources formed as buried waveguides.

Abstract: An optical transport network comprises a monolithic transmitter photonic integrated circuit (TxPIC) InP-based chip and a monolithic receiver photonic integrated circuit (RxPIC) InP-based chip.

Abstract: A method of in-wafer testing is provided for a monolithic photonic integrated circuit (PIC) formed in a semiconductor wafer where each such in-wafer circuit comprises two or more integrated electro-optic components, one of each in tandem forming a signal channel in the circuit. The method includes the provision of a first integrated photodetector at a rear end of each signal channel and a second integrated photodetector at forward end of each signal channel. Then, the testing is accomplished, first, by sequentially operating a first of a selected channel electro-optic component in a selected circuit to monitor light output from a channel via its first corresponding channel photodetector and adjusting its operating characteristics by detecting that channel electro-optic component output via its second corresponding channel photodetector to provide first calibration data.

Abstract: A method for forming and apparatus comprising a free space coupler region having a plurality of optical waveguides coupled to the space coupler region at an interface region, the waveguides converging with one another to the interface region, and a trench formed between adjacent waveguides, the depth of the trench or trenches extending from an outer point to the interface region and monotonically decreasing in depth from the outer point to the interface region.

Abstract: An arrayed waveguide grating (AWG) comprises at least two free space regions, a plurality of grating arms extending between the two space regions, a passivation layer formed over the arrayed waveguide grating and a plurality of inputs at least to one of the free space regions to receive a plurality of channel signals separated by a predetermined channel spacing. A depth of the passivation layer chosen by providing a TE to TM wavelength shift between TE and TM modes propagating through the arrayed waveguide grating being approximately less than or equal to 20% of a magnitude of the channel spacing.

Abstract: Disclosed are apparatus and methods of reducing insertion loss, passivation, planarization and in-wafer testing of integrated optical components and in-wafer chips in photonic integrated circuits (PICs).