Abstract: Embodiments of the present invention address deficiencies of the art in respect to backplane connectivity and provide a backplane connector for high density broadside differential signaling. In an embodiment of the invention, a backplane connector can be provided. The backplane connector can include a signal header assembly and a signal receptacle assembly. The signal header assembly can include pairs of differential signaling conductors arranged in columns for broadside signaling. Comparably, the signal receptacle assembly can include pairs of conductor receptacles arranged in columns to receive corresponding ones of the pairs of the differential signaling conductors.

Abstract: The melting point of the solder forming a controlled collapse chip connection is tailored by forming a thin metal cap of a metal such as palladium or silver on a solder bump. When the solder bump is melted during reflow, the metal cap dissolves into the solder. Because the resulting alloy has a higher melting point than the solder, subsequent reflow processing does not melt the chip join structure.

Abstract: Aluminum heatsinks are plated with a solderable layer and are overplated with a solder release layer. The release layer comprises a tin-lead-indium alloy. The heatsinks are mounted on individual IC modules or banks of IC modules that are interconnected to a printed circuit card. A mechanically compliant, thermally conductive adhesive is used to join the heatsinks to the modules. An oxide formed on the release layer readily bonds with the thermally conductive adhesive. In the event that heatsinks need to be removed to repair or rework the modules, local heat may be applied to melt the release layer to remove a heatsink without need for use of significant applied torque and normal forces. Because the release layer has a low melting point that affords easy separation from the adhesive layer, both component delaminations and the partial reflow or melting of solder joints on adjacent components are eliminated from the heatsink removal process.

Abstract: A printed circuit connector terminal pad coating technique is disclosed which functions as a single universal pad surface which supports multiple electrical connection practices including wirebonding, soldering, and wear resistant, pad on pad mechanical connection. The tri-plate surface treatment includes an initial diffusion resistant coating of nickel; an intermediate layer of hard, wear resistant noble or semi-noble metal that provides pad on pad connector reliability and affords a metallurgically stable solder joints and wirebond interfaces; and a final coating of soft gold. The intermediate layer may be pure palladium having a nominal thickness of 35 microinches or a layer of gold, hardened by cobalt, nickel, iron or a combination of these dopants to effect a hardness of 200 to 250 (Knoop scale). The use of a common surface treatment for the multiple attachment processes is implemented with a single masking step, rather than a sequence of selective masking, plating and stripping operations.

Abstract: A method for analyzing solder joint assemblies in devices such as solder bumped silicon chips, ball grid arrays or land grid arrays is disclosed. The method includes applying a dye solution to a device under test and then causing that dye solution to penetrate any interstices between any solder interconnect and the device under test, which also includes penetrating any fractures in any joints or joint failures. Next, the dye is dried or cured so as to provide ready analysis upon the analysis portion of the method. The device under test is then caused to be separated or fractured in such a way that a seam or border of a solder joint or an attachment border may be analyzed to identify any structural failure by visually analyzing where any dye has penetrated such structural failures.

Abstract: A direct chip attachment process and apparatus for aluminum wirebonding on copper circuitization are provided. After at least one integrated circuit chip is attached to a carrier, an aqueous cleaning solution containing citric and oxalic acid based additives is applied to the carrier and attached integrated circuit chip. Then a deionized water rinse is applied to the carrier and attached integrated circuit chip, followed drying for a set time period. Next wirebonding on copper circuitization carried by the carrier is performed.

Abstract: An electronics device has unpackaged chips or other small components mounted on a carrier and wire-bonded to carrier wiring traces. The rear chip faces have a layer of adhesive which overlies a layer of solder or other fusible material, and which adheres to a pad area of the carrier. To replace a chip, its solder layer is melted, and the chip and adhesive are pulled off. Reapplying an adhesive layer allows a new chip to be mounted on the carrier and bonded to the traces.

Abstract: The Droplet Emulsion Technique is used to produce droplets of bulk metal or metal alloys containing inoculant particles. Heterogeneous nucleation responses are then separated and identified with variances in inoculant chemistry, size, morphology, and surface conditions in the different droplets. Differential Thermal Analysis (DTA) is used to detect and to correlate thermal signals generated from as little as 50 droplets 75-100 .mu.m in size, allowing the separation of signals generated by a minor fraction of the total droplet population. Quenching treatments are used on the samples during thermal analysis to retain the original solidification microstructures produced from effective inoculation. Differences between droplet solidification microstructures preserved from the quenching treatments allow for visual identification of effective and ineffective inoculant particles.

Abstract: Disclosed is a circuit board and a process for the manufacture thereof providing a circuit board comprising a metal core having parallel first and second major faces and exhibiting high thermal and electrical conductivity. The circuit board includes electrical insulating layers of thermally conductive, dielectric material applied to the first and second major faces of the metal core. Protecting the dielectric layer and copper conductors is a solder mask layer applied to the dielectric layers and forming outward facing major surfaces. A plurality of insulated and grounded vias having electrically conductive interior rings connecting the major surfaces are provided through the board. Conductive sleeves within the vias are either electrically insulated from the metal core by dielectric material or in electrical contact to the metal core for grounding.