Patents by Inventor Mark Kassab

Mark Kassab has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210150112
    Abstract: A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.
    Type: Application
    Filed: October 28, 2020
    Publication date: May 20, 2021
    Inventors: Yu Huang, Janusz Rajski, Mark A. Kassab, Nilanjan Mukherjee, Jeffrey Mayer
  • Patent number: 11010523
    Abstract: One, two, or three test pattern generation and encoding processes are performed for a circuit design to generate compressed test patterns for one or two input channel numbers. The one, two, or three test pattern generation and encoding processes are configured to minimize active input channels for each of the compressed test patterns. A test pattern count for each of a plurality of input channel numbers is determined based on the compressed test patterns for the one or two input channel numbers, a number of active input channels for each of the compressed test patterns, and an assumption of similar input data volumes for different numbers of input channels. The test pattern count information can be employed to determine an optimal number of input channels for a test decompressor.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 18, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Yu Huang, Janusz Rajski, Mark A. Kassab, Wu-Tung Cheng
  • Patent number: 10977400
    Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 13, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
  • Patent number: 10955460
    Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: March 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
  • Publication number: 20200410065
    Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 31, 2020
    Inventors: Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
  • Patent number: 10788530
    Abstract: Various aspects of the disclosed technology relate to streaming data to circuit blocks in a circuit. A system for streaming data in a circuit comprises a first network comprising first data channels and first interface devices and a second network comprising second data channels and second interface devices. Each of the first interface devices is coupled to ports of one of circuit blocks in the circuit and configurable to transport a plurality of equal-sized data packets consecutively. Each of the second interface devices is coupled to one of the first interface devices and configurable to transport configuration data to the first interface devices. The configuration data comprise data for determining whether or not a first interface device is activated and data for determining which bit or bits of each of the plurality of data packets to be captured, replaced, or captured and replaced by an activated first interface device.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: September 29, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
  • Patent number: 10775436
    Abstract: Various aspects of the disclosed technology relate to using data throttling to generate streaming data for streaming networks in circuits. A plurality of equal-sized data packets to be transported consecutively in a network to the plurality of circuit blocks are generated. The number of bits in each of the plurality of equal-sized data packets assigned to a circuit block requiring longest data loading time is equal to the number of input ports of the circuit block, while the number of bits in each of the plurality of data packets assigned to each of the rest of the plurality of circuit blocks is equal to or smaller than the number of input ports of the each of rest of the plurality of circuit blocks, determined based on the longest data loading time and data loading time for the each of rest of the plurality of circuit blocks.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: September 15, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
  • Patent number: 10509073
    Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 17, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
  • Patent number: 10473721
    Abstract: Various aspects of the disclosed technology relate to streaming data for testing identical circuit blocks in a circuit. The system for streaming data comprises a first network for transporting equal-sized data packets consecutively and a second network for configuring interface devices of the first network. Each of the data packets comprises bits of test patterns and bits of good-machine test responses. Comparison bits (pass/fail status bits) of an identical circuit block instance may be unloaded directly or may merge with those from other identical circuit block instances to generate accumulated comparison bits which are unloaded. A sticky pass/fail bit may also be generated for each of the identical circuit block instances.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 12, 2019
    Assignee: MENTOR GRAPHICS CORPORATION
    Inventors: Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
  • Patent number: 10476740
    Abstract: Various aspects of the disclosed technology relate to generating streaming data and configuration data for streaming networks in circuits. Configuration information for transporting data in a first network to the plurality of circuit blocks in a circuit is determined based on information of the plurality of circuit blocks, information of the first network, the data, user-provided information, or any combination thereof. Sets of data packets are generated from the data based on the configuration information. Each set of the sets of data packets comprises equal-sized data packets to be transported consecutively in the first network. Configuration data to be transported in a second network in the circuit is also generated based on the configuration information. The configuration data comprises data for configuring first interface devices comprised in the first network.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 12, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
  • Patent number: 10234506
    Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 19, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
  • Patent number: 10120024
    Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: November 6, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
  • Publication number: 20180156867
    Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
    Type: Application
    Filed: October 2, 2017
    Publication date: June 7, 2018
    Applicant: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
  • Patent number: 9915702
    Abstract: Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: March 13, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Yu Huang, Mark A. Kassab, Janusz Rajski, Wu-Tung Cheng, Jay Babak Jahangiri
  • Publication number: 20180045780
    Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
    Type: Application
    Filed: July 31, 2017
    Publication date: February 15, 2018
    Applicant: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
  • Publication number: 20180017622
    Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
    Type: Application
    Filed: May 30, 2017
    Publication date: January 18, 2018
    Applicant: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
  • Patent number: 9778316
    Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: October 3, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
  • Patent number: 9720040
    Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: August 1, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
  • Patent number: 9664739
    Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 30, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rasjki, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
  • Patent number: 9651622
    Abstract: Various aspects of the disclosed technology relate to techniques of creating test templates for test pattern generation. Residual test cubes for a plurality of faults are first generated based on a signal probability analysis of a circuit design. Test templates are then generated based on merging the residual test cubes. Finally, a plurality of test patterns and/or compressed test cubes are generated based on one of the test templates.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: May 16, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Amit Kumar, Mark A. Kassab, Elham Moghaddam, Nilanjan Mukherjee, Jerzy Tyszer, Chen Wang