Patents by Inventor Mark Kassab
Mark Kassab has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10955460Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.Type: GrantFiled: March 16, 2011Date of Patent: March 23, 2021Assignee: Mentor Graphics CorporationInventors: Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
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Patent number: 10509073Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: July 31, 2017Date of Patent: December 17, 2019Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Continuous application and decompression of test patterns and selective compaction of test responses
Patent number: 10234506Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: GrantFiled: May 30, 2017Date of Patent: March 19, 2019Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Patent number: 10120024Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: GrantFiled: October 2, 2017Date of Patent: November 6, 2018Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
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Publication number: 20180156867Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: ApplicationFiled: October 2, 2017Publication date: June 7, 2018Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
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Publication number: 20180045780Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: July 31, 2017Publication date: February 15, 2018Applicant: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES
Publication number: 20180017622Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: ApplicationFiled: May 30, 2017Publication date: January 18, 2018Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Patent number: 9778316Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: GrantFiled: February 1, 2016Date of Patent: October 3, 2017Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
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Patent number: 9720040Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: July 20, 2015Date of Patent: August 1, 2017Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Continuous application and decompression of test patterns and selective compaction of test responses
Patent number: 9664739Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: GrantFiled: September 14, 2015Date of Patent: May 30, 2017Assignee: Mentor Graphics CorporationInventors: Janusz Rasjki, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Publication number: 20160320450Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: ApplicationFiled: February 1, 2016Publication date: November 3, 2016Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
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CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES
Publication number: 20160003907Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: ApplicationFiled: September 14, 2015Publication date: January 7, 2016Applicant: Mentor Graphics CorporationInventors: Janusz Rasjki, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Publication number: 20150323600Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Applicant: MENTOR GRAPHICS CORPORATIONInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Continuous application and decompression of test patterns and selective compaction of test responses
Patent number: 9134370Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: GrantFiled: September 9, 2013Date of Patent: September 15, 2015Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Patent number: 9086454Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: October 14, 2013Date of Patent: July 21, 2015Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20140047404Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: October 14, 2013Publication date: February 13, 2014Applicant: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES
Publication number: 20140006888Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: ApplicationFiled: September 9, 2013Publication date: January 2, 2014Applicant: MENTOR GRAPHICS CORPORATIONInventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Patent number: 8560906Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: October 31, 2011Date of Patent: October 15, 2013Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Continuous application and decompression of test patterns and selective compaction of test responses
Patent number: 8533547Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: GrantFiled: January 25, 2011Date of Patent: September 10, 2013Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Patent number: 8290738Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.Type: GrantFiled: March 16, 2011Date of Patent: October 16, 2012Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer