Patents by Inventor Mark Lamorey
Mark Lamorey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10243016Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes manufacturing the second wafer in accordance with a periodicity that matches the periodicity of the first wafer. The method further includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method also includes stacking the first wafer onto the second wafer. The first wafer includes logic circuitry, and the second wafer includes a backside illuminated image sensor.Type: GrantFiled: April 13, 2018Date of Patent: March 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Arvind Kumar, Mark Lamorey
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Patent number: 10236317Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer.Type: GrantFiled: January 11, 2018Date of Patent: March 19, 2019Assignee: International Business Machines CorporationInventors: Arvind Kumar, Mark Lamorey
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Publication number: 20180233526Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes manufacturing the second wafer in accordance with a periodicity that matches the periodicity of the first wafer. The method further includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method also includes stacking the first wafer onto the second wafer. The first wafer includes logic circuitry, and the second wafer includes a backside illuminated image sensor.Type: ApplicationFiled: April 13, 2018Publication date: August 16, 2018Inventors: Arvind Kumar, Mark Lamorey
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Patent number: 10002900Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer.Type: GrantFiled: July 21, 2017Date of Patent: June 19, 2018Assignee: International Business Machines CorporationInventors: Arvind Kumar, Mark Lamorey
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Publication number: 20180138228Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer.Type: ApplicationFiled: January 11, 2018Publication date: May 17, 2018Inventors: Arvind Kumar, Mark Lamorey
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Patent number: 9881956Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer using a bonding material.Type: GrantFiled: May 6, 2016Date of Patent: January 30, 2018Assignee: International Business Machines CorporationInventors: Arvind Kumar, Mark Lamorey
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Publication number: 20170323920Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer, using a copper-to-copper bonding process to bond the first wafer to the second wafer.Type: ApplicationFiled: July 21, 2017Publication date: November 9, 2017Inventors: Arvind Kumar, Mark Lamorey
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Publication number: 20170323919Abstract: A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes selecting a periodicity for the second wafer to be manufactured that matches the periodicity of the first wafer. The method further includes manufacturing the second wafer in accordance with the selected periodicity. The method also includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method additionally includes stacking the first wafer onto the second wafer using a bonding material.Type: ApplicationFiled: May 6, 2016Publication date: November 9, 2017Inventors: Arvind Kumar, Mark Lamorey
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Patent number: 8653662Abstract: A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.Type: GrantFiled: May 2, 2012Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Luke D. LaCroix, Mark Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Publication number: 20130292817Abstract: A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.Type: ApplicationFiled: May 2, 2012Publication date: November 7, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luke D. LaCroix, Mark Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone
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Patent number: 7791933Abstract: A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.Type: GrantFiled: December 21, 2007Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Mark Lamorey, Thomas Happ
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Patent number: 7719913Abstract: A sensing method for a memory cell as described herein includes selecting a memory cell. A first bias applied to the memory cell induces a first response in the memory cell. A second bias applied to the memory cell induces a second response in the memory cell, the second bias different from the first bias. The method includes determining a data value stored in the memory cell based on a difference between the first and second responses and a predetermined reference.Type: GrantFiled: September 12, 2008Date of Patent: May 18, 2010Assignees: Macronix International Co., Ltd., International Business Machines CorporationInventors: Hsiang-Lan Lung, Mark Lamorey
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Publication number: 20100067285Abstract: A sensing method for a memory cell as described herein includes selecting a memory cell. A first bias applied to the memory cell induces a first response in the memory cell. A second bias applied to the memory cell induces a second response in the memory cell, the second bias different from the first bias. The method includes determining a data value stored in the memory cell based on a difference between the first and second responses and a predetermined reference.Type: ApplicationFiled: September 12, 2008Publication date: March 18, 2010Applicants: Macronix International Co., Ltd., International Business Machines CorporationInventors: Hsiang-Lan Lung, Mark Lamorey
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Patent number: 7652914Abstract: A memory includes a bit line and a phase change element. A first side of the phase change element is coupled to the bit line. The memory includes a first access device coupled to a second side of the phase change element and a second access device coupled to the second side of the phase change element. The memory includes a circuit for precharging the bit line and one of selecting only the first access device to program the phase change element to a first state and selecting both the first access device and the second access device to program the phase change element to a second state.Type: GrantFiled: January 9, 2007Date of Patent: January 26, 2010Assignees: Qimonda North America Corp., International Business Machines Corporation, Macronix International Co., Ltd.Inventors: Thomas Nirschl, Roger Cheek, Mark Lamorey, Ming-Hsiu Lee
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Patent number: 7626860Abstract: A method and system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC). The method and system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.Type: GrantFiled: March 23, 2007Date of Patent: December 1, 2009Assignee: International Business Machines CorporationInventors: Mark Lamorey, Thomas Happ
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Publication number: 20090161416Abstract: A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Qimonda AGInventors: Mark Lamorey, Thomas Happ
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Patent number: 7541609Abstract: A memory cell includes a first electrode and a second electrode forming an opening. The opening is defined by a first sidewall, a second sidewall, and a surface extending between the first sidewall and the second sidewall. The memory cell includes phase change material contacting the first electrode and the first sidewall and the second sidewall. The memory cell includes isolation material electrically isolating the phase change material from the surface extending between the first sidewall and the second sidewall.Type: GrantFiled: November 17, 2006Date of Patent: June 2, 2009Assignees: International Business Machines Corporation, Qimonda North America Corp.Inventors: Thomas Nirschl, Mark Lamorey
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Publication number: 20090027943Abstract: A memory includes a first electrode, a second electrode, and a resistive memory element coupled between the first electrode and the second electrode. The memory includes a circuit configured to write a data value to the resistive memory element by sequentially applying a first signal from the first electrode to the second electrode and a second signal from the second electrode to the first electrode.Type: ApplicationFiled: July 24, 2007Publication date: January 29, 2009Inventors: Thomas Nirschl, Mark Lamorey
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Publication number: 20080232158Abstract: A method and system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC). The method and system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Inventors: Mark Lamorey, Thomas Happ
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Publication number: 20080165573Abstract: A memory includes a bit line and a phase change element. A first side of the phase change element is coupled to the bit line. The memory includes a first access device coupled to a second side of the phase change element and a second access device coupled to the second side of the phase change element. The memory includes a circuit for precharging the bit line and one of selecting only the first access device to program the phase change element to a first state and selecting both the first access device and the second access device to program the phase change element to a second state.Type: ApplicationFiled: January 9, 2007Publication date: July 10, 2008Inventors: Thomas Nirschl, Roger Cheek, Mark Lamorey, Ming-Hsiu Lee