Abstract: Secure operations within an integrated circuit are protected. In order to perform the protection a plurality of single event upset detectors are distributed within the integrated circuit. The single event upset detectors include bit-registers. Each of the plurality of the single event upset detectors is monitored for a single event upset. When a single event upset in any of the single event upset detectors is detected, an error condition is indicated.

Abstract: A multi-cycle, non-parallel DES encryption scheme that supports CBC, OFB, CFB, and ECB modes of operation. Three independent cipher stages are coupled together in series in order to implement a high-speed DES core. Sixteen cipher operations are required for DES encryption and decryption. Hence, the data is routed through the DES core five times. On the sixth pass, the encrypted/decrypted data is taken from the output of the first cipher stage. This output can then be used to encrypt/decrypt any subsequent input data. A different key is supplied to each of the cipher stages for each cycle.

Abstract: A method for encrypting and decrypting digital data. The digital data is initially latched by an input register. Sixteen separate cipher stages cascaded in series are used to encrypt the digital data. These cipher stages are operating at a maximum frequency limited only by the process technology. The encoded digital data from the last cipher stage is stored in an output register. The input and output registers are capable of being docked at an interface frequency that is different from that of the DES core's data frequency. After an appropriate number of cycles have elapsed, the output register is sampled. A programmable counter is used to indicate when the output register contains valid encrypted data.