Abstract: Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. The cell camouflaging covert gate leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. A comprehensive security analysis of the covert gate shows that it achieves high resiliency against SAT and test-based attacks at very low overheads. Models are derived to characterize the covert cells, and metrics are developed to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.

Abstract: Circuits and methods for protecting against intellectual property piracy and integrated circuit piracy from an untrusted third party are provided. A circuit can include an original circuit and an obfuscated circuit incorporated into the original circuit and changing the output of the original circuit, wherein the obfuscated circuit is configured to recover the output of the original circuit by modifying the obfuscated circuit. In addition, a method of manufacturing a semiconductor device can include designing a circuit including an original circuit and an obfuscated circuit, and fabricating the circuit, wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit by modifying the obfuscated circuit.

Abstract: A method of detecting hardware Trojans in an IC includes providing a golden IC layout data set or SEM image data taken at long dwelling time on an active area of the golden IC after polishing it from the backside. Next, the IC under authentication (IUA) sample is prepared for fast SEM imagining (shorter dwelling time) after backside thinning. Next step is to perform image processing on the IUA's SEM image, which includes histogram equalization with noise filtering using Gaussian and Median filters. In the last step, the IUA sample data with the shorter dwelling time is compared with the golden IC layout data or the golden image data from high quality (longer dwelling time) SEM scanning process. At the end the result of the comparison is used to identify hardware Trojans.

Abstract: An unclonable chipless radio frequency identification (RFID) tag and corresponding cross-registration methods of determining an identity and/or tag signature of an RFID tag are described. In an example embodiment, an unclonable chipless RFID tag comprises a first tag portion comprising one or more first conductive members unremovably secured to a dielectric item; and a second tag portion comprising packaging conductive pattern. The first tag portion and the second tag portion are in a static or fixed physical relationship with respect to one another.

Abstract: Various examples are provided related to power side-channel vulnerability assessment. In one example, a method includes identifying target registers in an IC design; generating input patterns associated with a target function that can generate a power difference in the target registers when processing the target function; determining a side-channel vulnerability (SCV) metric using the power difference produced by the input patterns; and identifying a vulnerability in the IC design using the SCV metric. Identification of the vulnerability allows for modification of the IC design at an early stage, which can avoid power side-channel attacks (e.g., DPA and CPA) in the fabricated IC design. The method can be used for pre-silicon power side-channel leakage assessment of IC designs such as, e.g., cryptographic and non-cryptographic circuits.

Abstract: Methods, apparatus and computer program product for protecting a confidential integrated circuit design process.

Abstract: Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. The cell camouflaging covert gate leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. A comprehensive security analysis of the covert gate shows that it achieves high resiliency against SAT and test-based attacks at very low overheads. Models are derived to characterize the covert cells, and metrics are developed to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.

Abstract: A pyramid structure to mitigate optical probing attacks in ICs by scrambling the measurements reflected by a laser pulse is disclosed. The pyramid structure is applied to selected areas at the bottom surface of the metal traces in metal layer to circumvent the extra silicon layer and thus minimize the changes to the conventional device structures. The pyramid structure includes randomized pyramids at nanometer scale. Optical simulation results show the pyramidized metal surface is able to prevent optical probing attacks. The fabrication of pyramids is CMOS compatible as well. Optical simulations are performed to analyze the impact these nano-scaled pyramids in a laser voltage probing attacking model. The nanopyramid can disturb the optical measurements enough to make the attacks practically infeasible. In addition, the nanopyramid structure countermeasure works in a passive mode without consuming any energy.

Abstract: A method of detecting hardware Trojans in an IC includes providing a golden IC layout data set or SEM image data taken at long dwelling time on an active area of the golden IC after polishing it from the backside. Next, the IC under authentication (IUA) sample is prepared for fast SEM imagining (shorter dwelling time) after backside thinning. Next step is to perform image processing on the IUA's SEM image, which includes histogram equalization with noise filtering using Gaussian and Median filters. In the last step, the IUA sample data with the shorter dwelling time is compared with the golden IC layout data or the golden image data from high quality (longer dwelling time) SEM scanning process. At the end the result of the comparison is used to identify hardware Trojans.

Abstract: A dynamically obfuscated scan chain (DOSC) includes a control module designed to control memory loading, a linear feedback shift register (LFSR), a dynamic Obfuscation Key generator configured to use LFSR to generate a ?-bit protected Obfuscation Key, in order to confuse and change the test data into an output scan vectors when the Obfuscation Key update is triggered. The DOSC also includes a shadow chain, configured to input the ?-bit protected Obfuscation Key generated by the LFSR, and output k ??×??-bit protected Obfuscation Keys, and obfuscated scan chains. The DOSC operating method includes: loading control vectors to LFSR from control module during initialization; generating the Obfuscation Key at an output of the LFSR; generating the Obfuscation Key bit by bit based at least in part on the shadow chain and the Obfuscation Key during a first scan clock after reset in order to confuse test patterns.

Abstract: A method of assessing vulnerability of Integrated Circuit (IC) can include: preparing a list of logic nets of the IC; obtaining rectangular segments from the logic nets; finding a milling exclusion area based on a covering wire; and superimposing the found milling exclusion area onto the rectangular segments of the logic nets. The milling exclusion area is an area that microprobing attack does not succeed without cutting off at least one of the rectangular segments.

Abstract: An unclonable chipless radio frequency identification (RFID) tag and corresponding cross-registration methods of determining an identity and/or tag signature of an RFID tag are described. In an example embodiment, an unclonable chipless RFID tag comprises a first tag portion comprising one or more first conductive members unremovably secured to a dielectric item; and a second tag portion comprising packaging conductive pattern. The first tag portion and the second tag portion are in a static or fixed physical relationship with respect to one another.

Abstract: Disclosed are various embodiments for detecting hardware Trojans through information flow security verification. A file comprising register transfer level (HDL) code for an intellectual property core is loaded from memory. An asset within the intellectual property core is identified. An integrity verification or confidentiality verification of the HDL code that represents the asset is performed. An integrity violation or confidentiality violation within the HDL code as a result of performance of the integrity verification or confidentiality violation on the HDL code that represents the asset is detected. A malicious control point or a malicious observation point linked to the asset is identified. Finally, a trigger circuit for a hardware Trojan is identified in response to identification of the malicious control point or malicious observation point.

Abstract: Circuits and methods for protecting against intellectual property piracy and integrated circuit piracy from an untrusted third party are provided. A circuit can include an original circuit and an obfuscated circuit incorporated into the original circuit and changing the output of the original circuit, wherein the obfuscated circuit is configured to recover the output of the original circuit by modifying the obfuscated circuit. In addition, a method of manufacturing a semiconductor device can include designing a circuit including an original circuit and an obfuscated circuit, and fabricating the circuit, wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit by modifying the obfuscated circuit.

Abstract: Methods and integrated circuit architectures for assuring the protection of intellectual property between third party IP providers, system designers (e.g., SoC designers), fabrication entities, and assembly entities are provided. Novel design flows for the prevention of IP overuse, IP piracy, and IC overproduction are also provided. A comprehensive framework for forward trust between 3PIP vendors, SoC design houses, fabrication entities, and assembly entities can be achieved, and the unwanted modification of IP can be prevented.

Abstract: A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied. The semiconductor device can further include a dummy via disposed on the first metal trace.

Abstract: Chipless RFID tags and methods of using the same are provided. Each RFID tag provided herein can generate a unique and unclonable (unclonable chipless RFID, or UCR) identifier from its intrinsically random manufacturing process. The UCR device can monitor increase in storage temperature beyond that which is appropriate for a specific commodity to which the device is attached.

Abstract: A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied. The semiconductor device can further include a dummy via disposed on the first metal trace.

Abstract: A method of assessing vulnerability of Integrated Circuit (IC) can include: preparing a list of logic nets of the IC; obtaining rectangular segments from the logic nets; finding a milling exclusion area based on a covering wire; and superimposing the found milling exclusion area onto the rectangular segments of the logic nets.

Abstract: Chipless RFID tags and methods of using the same are provided. Each RFID tag provided herein can generate a unique and unclonable (unclonable chipless RFID, or UCR) identifier from its intrinsically random manufacturing process. The UCR device can monitor increase in storage temperature beyond that which is appropriate for a specific commodity to which the device is attached.