Patents by Inventor Mark Meldrim
Mark Meldrim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10304749Abstract: In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.Type: GrantFiled: June 20, 2017Date of Patent: May 28, 2019Assignee: Intel CorporationInventors: Christopher W. Petz, Philip M. Campbell, Wei Yeeng Ng, Kunal Bhaskar Shrotri, Saurabh Keshav, John Mark Meldrim, Prakash Rau Mokhna Rau, Tom Jibu John
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Patent number: 10283524Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.Type: GrantFiled: December 20, 2017Date of Patent: May 7, 2019Assignee: Micron Technology, Inc.Inventors: Jordan D. Greenlee, Chet E. Carter, Collin Howder, John Mark Meldrim, Everett A. McTeer
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Publication number: 20190097017Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
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Publication number: 20190088671Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (h) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.Type: ApplicationFiled: September 20, 2017Publication date: March 21, 2019Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
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Patent number: 10170493Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.Type: GrantFiled: December 20, 2017Date of Patent: January 1, 2019Assignee: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, Everett A. McTeer
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Patent number: 10164044Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.Type: GrantFiled: April 16, 2015Date of Patent: December 25, 2018Assignee: Micron Technology, Inc.Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
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Publication number: 20180366386Abstract: In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Applicant: Intel CorporationInventors: Christopher W. Petz, Philip M. Campbell, Wei Yeeng Ng, Kunal Bhaskar Shrotri, Saurabh Keshav, John Mark Meldrim, Prakash Rau Mokhna Rau, Tom Jibu John
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Publication number: 20180308861Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Applicant: Micron Technology, Inc.Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
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Patent number: 10014319Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.Type: GrantFiled: August 17, 2017Date of Patent: July 3, 2018Assignee: Micron Technology, Inc.Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
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Patent number: 9773807Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.Type: GrantFiled: March 10, 2017Date of Patent: September 26, 2017Assignee: Micron Technology, Inc.Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
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Publication number: 20170117449Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.Type: ApplicationFiled: January 5, 2017Publication date: April 27, 2017Inventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
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Patent number: 9608185Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.Type: GrantFiled: April 25, 2014Date of Patent: March 28, 2017Assignee: Micron TechnologyInventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
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Publication number: 20160308018Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.Type: ApplicationFiled: April 16, 2015Publication date: October 20, 2016Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
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Publication number: 20160204205Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.Type: ApplicationFiled: January 6, 2016Publication date: July 14, 2016Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer
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Publication number: 20160093688Abstract: A multilayer source provides charge carriers to a multitier channel connector. The source includes a metal silicide layer on a substrate and a metal nitride layer between the metal silicide layer and the channel. The metal silicide and the metal nitride are processed without an intervening oxide layer between them. In one embodiment, the source further includes a silicon layer between the metal nitride layer and the channel. The silicon layer can also be processed without an intervening oxide layer. Thus, the source does not have an intervening oxide layer from the substrate to the channel.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer
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Patent number: 9299767Abstract: A multilayer source provides charge carriers to a multitier channel connector. The source includes a metal silicide layer on a substrate and a metal nitride layer between the metal silicide layer and the channel. The metal silicide and the metal nitride are processed without an intervening oxide layer between them. In one embodiment, the source further includes a silicon layer between the metal nitride layer and the channel. The silicon layer can also be processed without an intervening oxide layer. Thus, the source does not have an intervening oxide layer from the substrate to the channel.Type: GrantFiled: September 26, 2014Date of Patent: March 29, 2016Assignee: INTEL CORPORATIONInventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer
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Patent number: 9076888Abstract: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.Type: GrantFiled: December 21, 2006Date of Patent: July 7, 2015Assignee: Micron Technology, Inc.Inventors: Hasan Nejad, Thomas A. Figura, Gordon A. Haller, Ravi Iyer, John Mark Meldrim, Justin Harnish
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Patent number: 8962431Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.Type: GrantFiled: January 16, 2014Date of Patent: February 24, 2015Assignee: Micron Technology, Inc.Inventors: David H. Wells, John Mark Meldrim, Rita J. Klein
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Publication number: 20140234996Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.Type: ApplicationFiled: April 25, 2014Publication date: August 21, 2014Applicant: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
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Patent number: 8728930Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.Type: GrantFiled: June 30, 2011Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventors: David H. Wells, John Mark Meldrim, Rita J. Klein