Abstract: A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

Abstract: A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells.

Abstract: Sectors of data are stored in a non-volatile memory by writing all the sectors in a first order and subsequently writing all the sectors in a different, second order that is determined prior to the second writing. Sectors are stored in a non-volatile memory by writing the sectors using a first set of write operations and again writing the sectors using a second set of write operations that write one or more of the sectors twice. The first set writes each sector only once and the second set writes the sectors from outside the memory. The first set writes in a mode that couples the cells of the memory less than the second set. The first set writes less reliably than the second set.

Abstract: Methods, systems and devices for testing flash memory dies are disclosed. According to some embodiments, during the post-wafer sort stage of device manufacture, a plurality of flash memory devices, each of which includes a flash controller die and at least one flash memory die associated with a common housing, are subjected to a testing process, for examples, a batch testing process or a mass testing process. During testing, a respective flash controller residing on a respective flash controller die executes at least one test program to test one or more respective flash memory dies of the respective flash device. A testing system including at least 100 of the flash memory devices and a mass-testing board is disclosed. Furthermore, flash memory devices where the flash controller is operative to test one or more of the flash memory dies are disclosed. Exemplary testing includes but is not limited to bad block testing.

Abstract: A method of storing data by providing a flash memory device including a plurality of memory cells; each of the memory cells is capable of storing data bits. First data bits are stored into memory cells used for storing M bits per cell, the memory cells are allocated to a page of the memory. Second data bits are stored into other memory cells, the other memory cells used for storing N bits per cell are allocated to the page and upon storing of the first data bits and upon storing the second data bits, the page uses at the same time at least one of the memory cells with M bits per cell and at least one of the other memory cells with N bits per cell with N less than M.

Abstract: Sectors of data are stored in a non-volatile memory by writing all the sectors in a first order and subsequently writing all the sectors in a different, second order that is determined prior to the second writing. Sectors are stored in a non-volatile memory by writing the sectors using a first set of write operations and again writing the sectors using a second set of write operations that write one or more of the sectors twice. The first set writes each sector only once and the second set writes the sectors from outside the memory. The first set writes in a mode that couples the cells of the memory less than the second set. The first set writes less reliably than the second set.

Abstract: To store N bits of M?2 logical pages, the bits are interleaved and the interleaved bits are programmed to ?N/M? memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the ?N/M? cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.