Abstract: A system including a first core to execute instructions associated with an application at a first speed based on a first instruction set and a second core to execute the instructions associated with the application at a second speed based on a second instruction set. The first speed is greater than the first speed. The second instruction set is a subset of the first instruction set. A first memory stores an operating system. The operating system includes a kernel that provides services to the application. A core switching module loads into a second memory after the operating system is booted, where the second memory is separate from the first memory, switches execution of the instructions associated with the application between the first core and the second core, and switches the execution of the instructions associated with the application between the first core and the second core transparently to the operating system.

Abstract: A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.

Abstract: A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

Abstract: A method including: assigning identifiers to respective domains, where each of the domains is allocated a corresponding set of resources, and where the resources in the sets of resources are accessible at respective physical addresses; storing permissions to access the physical addresses, where each of the permissions indicates which of the physical addresses one or more of the domains are permitted to access. The method also includes: assigning a code to a first domain, where the code includes instructions, and where each of the instructions includes a corresponding one of the physical addresses; tagging each of the instructions by adding the identifier assigned to the first domain to each of the instructions; and during execution of each of the instructions, comparing the identifier included in the corresponding instruction to one of the permissions; and based on the comparison, permitting access to the set of resources allocated to the first domain.

Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

Abstract: A method including: assigning identifiers to respective domains, where each of the domains is allocated a corresponding set of resources, and where the resources in the sets of resources are accessible at respective physical addresses; storing permissions to access the physical addresses, where each of the permissions indicates which of the physical addresses one or more of the domains are permitted to access. The method also includes: assigning a code to a first domain, where the code includes instructions, and where each of the instructions includes a corresponding one of the physical addresses; tagging each of the instructions by adding the identifier assigned to the first domain to each of the instructions; and during execution of each of the instructions, comparing the identifier included in the corresponding instruction to one of the permissions; and based on the comparison, permitting access to the set of resources allocated to the first domain.

Abstract: In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.

Abstract: A method and apparatus configure a trusted domain and a plurality of isolated domains in a processor core. Each isolated domain is assigned a unique domain identifier. One or more resources are associated with each isolated domain. The associations are stored as permissions to access physical addresses of resources. Code to be executed by a hardware device is assigned to one of the isolated domains. The domain identifier for the assigned isolated domain is written to the hardware device. When the hardware device executes the code, each instruction is logically tagged with the domain identifier written to the hardware device. An instruction includes request to access a physical address. The hardware device compares the domain identifier of the instruction with the permissions. If the permissions allow the domain identifier to access the physical address, then access to the resource at the physical address is allowed. Access is otherwise blocked.

Abstract: A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.

Abstract: A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The spoke modules include a plurality of interface circuits each having a hardware address. A memory module stores the hub software and hub data and configuration data. The hub software includes a plurality of driver modules corresponding to the plurality of interface circuits. The processing module executes boot firmware to configure the plurality of driver modules based on the hardware address of each of the plurality of interface circuits.

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

Abstract: A method for operating a host device includes comparing a predetermined response of a peripheral device to a response token received from the peripheral device. The predetermined response and the response token are generated based on a first command transmitted from the host device to the peripheral device. The method further includes controlling a transfer of first data from a first memory to a peripheral control module based on the comparison between the predetermined response and the response token without interrupting a host control module, and selectively passing interrupts to the host control module when the predetermined response does not match the response token.

Abstract: In one embodiment the present invention includes a method and apparatus for enabling a main core and one or more co-processors to operate in a de-coupled mode, thereby facilitating the execution of two or more instruction threads in parallel. A co-processor, according to an embodiment of the invention, has a coupling manager including a loop buffer for storing instructions which can be independently fetched and executed by the co-processor when operating in de-coupled mode. In addition, the coupling manager includes a loop descriptor and a counter/condition descriptor. The loop descriptor and condition descriptor work in conjunction with one another to determine what, if any, action should be taken when a co-processor is in a particular processing state, for example, as indicated by a counter keeping track of loop processing.

Abstract: In some embodiments, a method for supporting multiple devices on a high speed physical link may be described. An embedded device may assert a link request pin to request to transmit data on a multi-point communications link that may serve a plurality of embedded devices. A controlling device may receive the link request signal. When the controlling device finishes sending data on the link, it may address the plurality of embedded devices in a round robin format and may determine which device asserted the link request pin. The embedded device that asserted the link request pin may send an acknowledgement signal to the controlling device when it is addressed.

Abstract: Controlling a power supply which supplies a voltage to target circuit of an integrated circuit. An adjustable delay line powered by the supply voltage is co-located on the IC with the target circuit. The adjustable delay line is subjected to substantially the same operating conditions as the target circuit. A control unit measures a delay time of the adjustable delay line. Based on the measured delay time, the control unit outputs a control signal by which the power supply adjusts the supply voltage. The adjustable delay line comprises multiple distinct delay elements, each with delay properties and responsivity to changes in operating conditions. Each delay element emulates delay properties of physical elements (e.g., gates and wires) in the target circuit. In this manner, power consumption may be reduced, while still maintaining proper operation of the target circuit.