Abstract: A wireless device dynamically programs a control register for a command-chain driven DMA device. The control register stores a beginning address of the linked list of commands and a secure bit. The secure bit is set if the transaction writing register is secure and a bit in the data being written into the register is set. DMA devices and other bus-mastering peripherals perform tasks described via a command chain that has access to secure resources when the processor is operating in the secure mode and the secure bit is set.

Abstract: A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

Abstract: A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode.

Abstract: A memory controller partitions memory into secure partitions and non-secure partitions.

Abstract: A method and system for rendering a frame to be displayed on a screen includes a memory-sink mechanism configured to store a copy of a screen image in memory, a snoop mechanism configured to monitor a system parameter, a controller configured to switch between first and second operation modes in response to the snoop mechanism detecting a change to the system parameter, and a rendering mechanism to retrieve the copy of the screen image when the system operates in the second mode of operation.

Abstract: A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.

Abstract: A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.

Abstract: During debug operations in one embodiment of a trusted subsystem, passwords may be used to enable and disable access to selected areas, and to make access by different entities mutually exclusive. In another embodiment, programmable units may be used to define what the selected areas of access are for debug operations.

Abstract: Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state (e.g., “exclusive” or “shared”) are provided. In one embodiment, a first cache holds the memory block in an “exclusive” state prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache. The state of the block in the first cache changes from “exclusive” to “shared.” In another embodiment, a processor associated with a third cache attempts to read the block from the main memory while the first cache and the second both hold the block in the “shared” state. Either the first cache or the second cache wins an arbitration and supplies the block to the third cache.

Abstract: Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state (e.g., “exclusive” or “shared”) are provided. In one embodiment, a first cache holds the memory block in an “exclusive” state prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache. The state of the block in the first cache changes from “exclusive” to “shared.” In another embodiment, a processor associated with a third cache attempts to read the block from the main memory while the first cache and the second both hold the block in the “shared” state. Either the first cache or the second cache wins an arbitration and supplies the block to the third cache. In both embodiments, communications with main memory and power consumption are reduced.

Abstract: A communications interface is disclosed and claimed. The communications interface comprises a bus interface couplable to a bus and a plurality of transmit channels coupled to the bus interface. A transmit control block is coupled to the plurality of transmit channels and a plurality of receive channels are coupled to be bus interface. A receive control block is coupled to the plurality of receive control channels.

Abstract: In a data processing system a number of processing nodes share resources. Access to the shared resources is controlled by semaphores, each node having a local copy of all the semaphores. Nodes may acquire ownership of semaphores. When a node requires a semaphore operation on a particular semaphore, a semaphore message is broadcast to all the nodes instructing them to perform the semaphore operation on their local copies of the semaphore. If the semaphore is unowned, the node must suspend the semaphore operation until the message returns, so as to ensure correct chronology for the semaphore operation. If, however, the semaphore owned by this node, the node can perform the semaphore operation without waiting for the message to return. This speeds up the semaphore mechanism. If the semaphore is owned by another node, that other node relinquishes ownership so that the semaphore operation can be performed.