Abstract: An integrated circuit comprises a plurality of functional units, wherein a first functional unit comprises processing circuitry and a delay circuit coupled to the processing circuitry. The delay circuit is configured to receive signals from a plurality of directions, wherein the first functional unit receives a message from one direction and non-data from remaining directions. The delay circuit performs an OR operation on the signals to determine the message. The delay circuit delays the message for a predetermined duration based on a first distance between the first functional unit and a second functional unit that transmits the message and a second distance between the second functional unit and a functional unit farthest away from the second functional unit. The delay circuit releases the message to the processing circuitry for processing.

Abstract: An integrated circuit includes a set of functional units having at least a first functional unit and a second functional unit. The first functional unit includes first processing circuitry and a first circuit coupled to the first processing circuitry to receive a message from the second functional unit of the set of functional units. The first circuit is further to delay the message for the first processing circuitry for a predetermined duration, where the predetermined duration is based at least in part on a first value representing a first distance between the first functional unit and the second functional unit and a second value representing a second distance between the second functional unit and a functional unit of the set of functional units that is farthest away from the second functional unit.

Abstract: A system includes a functional unit having a processor and address management circuitry. The address management circuitry is to receive a request from the processor, where the request is associated with a boot process initialized at the processor. The address management circuitry is to determine a bit stored at the address management circuitry has a first value indicating to associate the request with a first node identifier associated with a memory region storing data associated with the boot process instead of a second node identifier associated with nodes storing physical locations associated with a memory address of the request. The address management circuitry can further transmit the request with the first node identifier to logic at a first node coupled to the memory region responsive to determining the bit has the first value.

Abstract: A system includes a functional unit having a processor and address management circuitry. The address management circuitry is to receive a request from the processor, where the request is associated with a boot process initialized at the processor. The address management circuitry is to determine a bit stored at the address management circuitry has a first value indicating to associate the request with a first node identifier associated with a memory region storing data associated with the boot process instead of a second node identifier associated with nodes storing physical locations associated with a memory address of the request. The address management circuitry can further transmit the request with the first node identifier to logic at a first node coupled to the memory region responsive to determining the bit has the first value.

Abstract: A device includes a first data storage circuit among multiple data storage circuits, an arbiter circuit coupled to the multiple data storage circuits, the arbiter circuit to determine that a value of the first data storage circuit has changed, an encoder circuit coupled to the arbiter circuit, the encoder circuit to encode first information pertaining to the value of the first data storage circuit that has changed into a virtual wire waveform, and a transmitter to transmit the virtual wire waveform in a mesh message over a mesh network.

Abstract: A transceiver for sending and receiving data packets on a communication channel. The transceiver receives a first request packet including a plurality of information fields having a first type of operation to be performed on a memory device and a first address. The transceiver stores the first type of operation and the first address in a memory associated with the transceiver, and sends to a target device, the first request packet with the first address. The transceiver then receives a second request packet, including a second address in the memory device, and determines, based on the first type of operation, the first address, and the second address, that the second request packet is part of a sequence of request packets to the target device. The transceiver then eliminates, in a header of the second request packet, a portion of the second address to form a third request packet and sends the third request packet to the target device.

Abstract: Various embodiments include techniques for storing data in a repurposed cache memory in a computing system. The disclosed techniques include a system level cache controller that processes a memory operation for a processing unit. The controller and the processing unit communicate over a network-on-chip. To process the memory operation, the controller selects a repurposed cache memory from a pool of active cache memories associated with processing units that are inoperable and/or are in a low-power state. To select the repurposed cache memory, the controller generates a candidate vector that identifies the position of the requesting processing unit relative to the controller. The candidate vector enables the controller in selecting a repurposed cache memory that is, for example, on the shortest path between the processing unit and the controller. These techniques result in a lower latency, and improved memory performance, relative to prior conventional techniques.

Abstract: A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.

Abstract: A system includes tiles arranged in a configurable topology. A first tile includes memory and one or more processing devices to: receive a first message including a coordinate identifier of a target tile, the coordinate identifier reflecting a location of the target tile; update a configuration value associated with the target tile based on the coordinate identifier, and transmit a second message to the target tile based on the configuration value.

Abstract: Various embodiments include techniques for storing data in a repurposed cache memory in a computing system. The disclosed techniques include a system level cache controller that processes a memory operation for a processing unit. The controller and the processing unit communicate over a network-on-chip. To process the memory operation, the controller selects a repurposed cache memory from a pool of active cache memories associated with processing units that are inoperable and/or are in a low-power state. To select the repurposed cache memory, the controller generates a candidate vector that identifies the position of the requesting processing unit relative to the controller. The candidate vector enables the controller in selecting a repurposed cache memory that is, for example, on the shortest path between the processing unit and the controller. These techniques result in a lower latency, and improved memory performance, relative to prior conventional techniques.

Abstract: A system including an array of functional units connected via a two-dimensional mesh network is described. A first functional unit in the array of function units includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including generating a node identifier identifying a second functional unit in the array of functional units, and transmitting, over the two-dimensional mesh network, the node identifier identifying the second functional unit in the array of functional units. The node identifier may include a mesh interface component and a port identifier, and one or more information elements selected from the group consisting of a payload, a target node identifier, a target type identifier, an information type identifier, a linear identifier, and a protocol identifier.

Abstract: A system includes a functional unit having a processor and address management circuitry. The address management circuitry is to receive a request from the processor, where the request is associated with a boot process initialized at the processor. The address management circuitry is to determine a bit stored at the address management circuitry has a first value indicating to associate the request with a first node identifier associated with a memory region storing data associated with the boot process instead of a second node identifier associated with nodes storing physical locations associated with a memory address of the request. The address management circuitry can further transmit the request with the first node identifier to logic at a first node coupled to the memory region responsive to determining the bit has the first value.

Abstract: An integrated circuit includes a set of functional units having at least a first functional unit and a second functional unit. The first functional unit includes first processing circuitry and a first circuit coupled to the first processing circuitry to receive a message from the second functional unit of the set of functional units. The first circuit is further to delay the message for the first processing circuitry for a predetermined duration, where the predetermined duration is based in part on a first value representing a first distance between the first functional unit and the second functional unit and a second value representing a second distance between the second functional unit and a functional unit of the set of functional units that is farthest away from the second functional unit.

Abstract: A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.

Abstract: A system including an array of functional units connected via a two-dimensional mesh network is described. A first functional unit in the array of function units includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including generating a node identifier identifying a second functional unit in the array of functional units, and transmitting, over the two-dimensional mesh network, the node identifier identifying the second functional unit in the array of functional units. The node identifier may include a mesh interface component and a port identifier, and one or more information elements selected from the group consisting of a payload, a target node identifier, a target type identifier, an information type identifier, a linear identifier, and a protocol identifier.

Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an “Owned” state and a Forward state together with protocol mechanism for handling various memory requests.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also discussed are techniques to add new capabilities to protocols, such as the CHI protocol to achieve “Total Store Order” (TSO) among multiple devices, such as PCI Express devices, in a cost effective manner.

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an “Owned” state and a Forward state together with protocol mechanism for handling various memory requests.