Abstract: In general, in one aspect, the disclosure describes passing work, such as a packet, between threads of a multi-threaded system.

Abstract: A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.

Abstract: Instruction-assisted cache management for efficient use of cache and memory. Hints (e.g., modifiers) are added to read and write memory access instructions to identify the memory access is for temporal data. In view of such hints, alternative cache policy and allocation policies are implemented that minimize cache and memory access. Under one policy, a write cache miss may result in a write of data to a partial cache line without a memory read/write cycle to fill the remainder of the line. Under another policy, a read cache miss may result in a read from memory without allocating or writing the read data to a cache line. A cache line soft-lock mechanism is also disclosed, wherein cache lines may be selectably soft locked to indicate preference for keeping those cache lines over non-locked lines.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for using the same memory type for both error check and non-error check systems. In an embodiment, a memory device is capable of operating in an error check mode and in a non-error check mode. The memory device includes an output having N error check bit paths for every M data bit paths. In one embodiment, the memory device is to transfer N error check bits with a corresponding M data bits, if the memory device is operating in an error check mode. Other embodiments are described and claimed.

Abstract: In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.

Abstract: In general, in one aspect, the disclosure describes a method that includes issuing, by a first thread at a first programmable unit of a set of multiple multi-threaded programmable units integrated within a single die, a request for a lock associated with data. The method also includes receiving, by the first thread, a grant for the lock and identification of a second thread to receive a grant for the lock after the lock is released by the first thread. The first thread initiates transfer of the data associated with the lock to the one of the multiple multi-threaded programmable units executing the second thread and releases the lock.

Abstract: In general, in one aspect, the disclosure describes a processor that includes multiple multi-threaded programmable units integrated on a single die. The die also includes circuitry communicatively coupled to the programmable units that reorders and grants lock requests received from the threads based on an order in which the threads requested insertion into a sequence of lock grants.

Abstract: Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I/O agents that issue atomic transactions to access and/or modify data stored in a shared memory space accessed via the memory interface unit. The host interface unit interfaces to a front-side bus (FSB) to which one or more processors may be coupled. In response to an atomic transaction issued by an I/O agent, the transaction is forked into two interdependent processes. Under one process, an inbound write transaction is injected into the host interface unit, which then drives the FSB to cause the processor(s) to perform a cache snoop. At the same time, an inbound read transaction is injected into the memory interface unit, which retrieves a copy of the data from the shared memory space.

Abstract: Techniques that may be utilized in a multiprocessor system are described. In one embodiment, one or more signals are generated to indicate that a breakpoint instruction is executed by one of the plurality of processors in the multiprocessor system.

Abstract: Techniques that may be utilized in a multiprocessor computing system are described. In one embodiment, a request from a thread includes a credit parameter that may be used to update a credit register of a ring manager.

Abstract: The disclosure describes techniques used by one or more producers and consumers of one or more rings.

Abstract: A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage.

Abstract: A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is transferred over a first bus from processing element to processing element.

Abstract: Systems and methods for dynamically changing ring size in network processing are disclosed. In one embodiment, a method generally includes requesting a free memory block from a free block pool manager by a ring manager for a corresponding ring when a first memory block is filled, receiving an address of a free memory block from the free block pool manager in response to the request from the ring manager, storing the address of the free memory block in the first memory block by the ring manager, the storing linking the free memory block to the first memory block as a next linked memory block to the first memory block, and repeating the requesting, receiving and storing for each additional linked memory blocks. An external service thread may be assigned to fulfill block fill-up requests from the free block pool manager.

Abstract: Techniques for arbitrating and scheduling thread usage in multi-threaded compute engines. Various schemes are disclosed for allocating compute (execution) usage of compute engines supporting multiple hardware contexts. The schemes include non-pre-emptive (cooperative) round-robin, priority-based round-robin with pre-emption, time division, cooperative round-robin with time division, and priority-based round-robin with pre-emption and time division. Aspects of the foregoing schemes may also be combined to form new schemes. The schemes enable finer control of thread execution in pipeline execution environments, such as employed for performing packet-processing operations.

Abstract: Systems and methods are disclosed for supporting virtual microengines in a multithreaded processor, such as a microengine running on a network processor. In one embodiment code is written for execution by a plurality of virtual microengines. The code is than compiled and linked for execution on a physical microengine, at which time the physical microengine's threads are assigned to thread groups corresponding to the virtual microengines. Internal next neighbor rings are allocated within the physical microengine to facilitate communication between the thread groups. The code can then be loaded onto the physical microengine and executed, with each thread group executing the code written for its corresponding virtual microengine.

Abstract: Data is enqueued and dequeued using a block-based queuing structure.

Abstract: A memory controller system includes a memory command storage module to store commands for a plurality of memory banks. The system includes a plurality of control mechanisms, each of which includes first and second pointers, to provide, in combination with a next field in each module location, a link list of commands for a given one of the plurality of memory banks.

Abstract: Method and apparatus to manage flow control for a network device are described.

Abstract: In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to data specified by a single instruction of a processing element specifying an access to data.