Abstract: Filter media comprising non-woven fiber webs having one or more advantageous physical properties are generally described. In some embodiments, a filter media and/or non-woven fiber web described herein comprises a combination of fibers that results in enhanced physical properties. For example, the non-woven fiber web may comprise a combination of fiber types that is advantageous, such as a combination comprising fibrillated fibers, glass fibers, and/or binder fibers. In some cases, the filter media and/or non-woven fiber web comprising the combination of fibers may be formed into undulations (e.g., by a creping and/or microcreping process) to further enhance the physical properties of the filter media and/or non-woven fiber.

Abstract: Filter media including out-of-plane solid elements are generally described. Inventive methods of forming them and uses thereof are also described.

Abstract: Valve assembly for a pump, the valve assembly including: a valve seat having a valve face (60), a flexible valve having a sealing portion for abutting the valve face (60), and at least a fluid pathway (66, 68, 70) from an interior of the valve seat to an exterior of the valve seat that serves as a leak flow path for fluid when the valve is in the closed position to reduce pressure build up on the valve. In this way, the vacuum inside the pump can be released when the value is in the closed position and the pump is stopped, thereby allowing the pump to start/restart due to reduced pressure build up on a side of the valve abutting the valve face. A pump or compressor including such a valve assembly is also disclosed.

Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.

Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

Abstract: Valve assembly for a pump, the valve assembly including: a valve seat having a valve face (60), a flexible valve having a sealing portion for abutting the valve face (60), and at least a fluid pathway (66, 68, 70) from an interior of the valve seat to an exterior of the valve seat that serves as a leak flow path for fluid when the valve is in the closed position to reduce pressure build up on the valve. In this way, the vacuum inside the pump can be released when the value is in the closed position and the pump is stopped, thereby allowing the pump to start/restart due to reduced pressure build up on a side of the valve abutting the valve face. A pump or compressor including such a valve assembly is also disclosed.

Abstract: Filter media, as well as related assemblies, systems and methods. Filter media may contain one or more layers formed of a meltblown material.

Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.

Abstract: Filter media, as well as related assemblies, systems and methods. Filter media may contain one or more layers formed of a meltblown material.

Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

Abstract: According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.

Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

Abstract: A real time gamma-ray signature/source identification method and system using principal components analysis (PCA) for transforming and substantially reducing one or more comprehensive spectral libraries of nuclear materials types and configurations into a corresponding concise representation/signature(s) representing and indexing each individual predetermined spectrum in principal component (PC) space, wherein an unknown gamma-ray signature may be compared against the representative signature to find a match or at least characterize the unknown signature from among all the entries in the library with a single regression or simple projection into the PC space, so as to substantially reduce processing time and computing resources and enable real-time characterization and/or identification.

Abstract: A discussion of a dynamic configuration for a prefetcher is proposed. For example, a thread specific latency metric is calculated and provides dynamic feedback to the software on a per thread basis via the configuration and status registers. Likewise, the software can optionally use the information from the registers to dynamically configure the prefetching behavior and allows the software to be able to both query the performance and configure the prefetcher.

Abstract: The invention provides 4,5-epoxymorphinan or a derivative thereof, a morphinan or a derivative thereof, or a pharmaceutical salt or a prodrug thereof. The present invention also provides compositions comprising the same, and methods for using the same. In particular, the invention relates to TLR antagonistic opioids and methods for using the same.