Patents by Inventor Mark S. Styduhar

Mark S. Styduhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040222864
    Abstract: An apparatus for providing power control to a real-time clock oscillator is disclosed. The apparatus includes a clock oscillator, a set of current limiting resistors and a set of latches. The current limiting resistors are coupled between a power supply and the clock oscillator. Coupled to the clock oscillator and the current limiting resistors, the latches control the current limiting resistors to limit the amount of current flowing from the power supply to the clock oscillator such that the power consumption by the clock oscillator is minimized.
    Type: Application
    Filed: May 5, 2003
    Publication date: November 11, 2004
    Applicant: International Business Machines Corporation
    Inventor: Mark S. Styduhar
  • Publication number: 20030132786
    Abstract: A method and structure for comparing an input signal to a reference signal using a comparator comprises a circuit for setting a trip point of a rising edge of an input signal according to a value of an external voltage reference; and at least two transistors, in the circuit, for setting a trip point of a falling edge of an input signal, according to a width-to-length ratio of the at least two transistors. Moreover, the at least two transistors comprises a first transistor of length (Lx) and a width of (Wx); and a second transistor of length (Ly) and a width of (Wy), wherein the width-to-length ratio equals (WxLy)/(WyLx). The trip point of a falling edge of an input signal increases (decreases) by increasing (decreasing) the width-to-length ratio.
    Type: Application
    Filed: January 17, 2002
    Publication date: July 17, 2003
    Applicant: International Business Machines Corporation
    Inventor: Mark S. Styduhar
  • Patent number: 6549150
    Abstract: An integrated test structure adapted to facilitate manufacturing verification of microelectronic devices such as Digital to Analog Converters (DAC) is disclosed. The test circuitry and the Circuit Under Test (CUT) are placed on an IC along with an arbitrary amount of digital logic, which drives the input of the CUT. These inputs are translated into an analog output. During a manufacturing test, this output is measured in order to determine that the IC has been manufactured correctly. The analog input of the circuit is coupled to the analog output of the DAC. The digital output of the test circuitry is coupled to the digital logic on the IC. This configuration comprises a Built In Self Test (BIST) structure. The invention allows BIST by eliminating the need to measure the analog output of the DAC external to the IC, and enables testing the CUT by using standard digital BIST techniques.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: April 15, 2003
    Assignee: International Business Machines Corporation
    Inventors: Raymond J. Bulaga, John K. Masi, Patrick W. Miller, Mark S. Styduhar, Donald L. Wheater
  • Publication number: 20030063019
    Abstract: An integrated test structure adapted to facilitate manufacturing verification of microelectronic devices such as Digital to Analog Converters (DAC) is disclosed. The test circuitry and the Circuit Under Test (CUT) are placed on an IC along with an arbitrary amount of digital logic, which drives the input of the CUT. These inputs are translated into an analog output. During a manufacturing test, this output is measured in order to determine that the IC has been manufactured correctly. The analog input of the circuit is coupled to the analog output of the DAC. The digital output of the test circuitry is coupled to the digital logic on the IC. This configuration comprises a Built In Self Test (BIST) structure. The invention allows BIST by eliminating the need to measure the analog output of the DAC external to the IC, and enables testing the CUT by using standard digital BIST techniques.
    Type: Application
    Filed: September 17, 2001
    Publication date: April 3, 2003
    Inventors: Raymond J. Bulaga, John K. Masi, Patrick W. Miller, Mark S. Styduhar, Donald L. Wheater
  • Patent number: 5396636
    Abstract: An inexpensive and low power consumption power control unit that does not require a separate interface or network. In the power off state only a detector and a power controller require power, this power is supplied from a power source. Upon detection of traffic a frame decoder is powered up to receive frames. When the link is quiet, the decoder is powered down while the power controller and receiver remain powered and await further traffic.
    Type: Grant
    Filed: October 21, 1991
    Date of Patent: March 7, 1995
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Gallagher, Karl H. Hoppe, Anthony J. Perri, Mark S. Styduhar, Jordan M. Taylor, Bert W. Weidle