Abstract: A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

Abstract: A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also include planarizing a surface of the interlayer dielectric.

Abstract: A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.

Abstract: In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer; and forming a high-K insulating layer over the p-type polysilicon layer.

Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming a first set of memory cell gates over the charge trapping dielectric in the core region; forming a conformal insulation material layer around the first set of memory cell gates; and forming a second set of memory cell gates in the core region, wherein each memory cell gate of the second set of memory cell gates is adjacent to at least one memory cell gate of the first set of memory cell gates, each memory cell gate of the first set of memory cell gates is adjacent at least one memory cell gate of the second set of memory cell gates, and the conformal insulation material layer is positioned between each adjacent memory cell gate.

Abstract: A non-volatile memory device includes a number of memory cells, parts of which are delineated by insulators. The insulators each include both a lower trench-fill insulator portion in a trench in the substrate, and an upper protruding portion that protrudes from the substrate. Between each pair of adjacent protruding insulator portions there is a pair of floating gates, the floating gates in contact with respective of the protruding insulator portions. There is a space or gap between the floating gates, such that a portion of a control gate enters therein, separated from the substrate by only an interpoly dielectric such as an oxide-nitride-oxide (ONO) stack, and a tunnel oxide. By storing charge on the floating gates, the conductivity of a channel between the floating gates may be altered. For example, conductivity through the channel may be “pinched off” by storing charge on the floating gates.

Abstract: A method of manufacturing for a Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited. A disposable anti-reflective coating (ARC) material and a photoresist material are deposited followed by processing to form a patterned photoresist material and a patterned ARC material. The hard mask material is processed to form a patterned hard mask material. The patterned photoresist is removed and then the patterned ARC without damaging the patterned hard mask material or the wordline material. The wordline material is processed using the patterned hard mask material to form a wordline and the patterned hard mask material is removed without damaging the wordline or the charge-trapping dielectric material.

Abstract: A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.

Abstract: A method of fabricating an improved flash memory device, having shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided, by first creating the shallow trench isolation using a hard mask; then creating the LOCOS isolation; and subsequently etching to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.

Abstract: An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetallic dielectric layer placed over the HTO layer. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The additional first and second side walls reduce current leakage between core stacks and the tungsten plug and help to protect the stacks during fabrication.

Abstract: A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.

Abstract: A method for making a semiconductor structure, includes patterning a photoresist layer to form both a zero marks pattern and a well implant mask pattern. The photoresist layer is on a region of a substrate.

Abstract: The present invention provides processes for doping and saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, word lines are doped prior to patterning the poly layer from which the word lines are formed in the core region. Thereby, the poly layer protects the substrate between the word lines from doping that could cause shorting between bit lines. According to another aspect of the invention, word lines are exposed while spacer material, dielectric, or like material protects the substrate between word lines. The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines even in virtual ground arrays where there are no oxide island isolation regions between bit lines.

Abstract: The present invention provides processes for doping and saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, word lines are doped prior to patterning the poly layer from which the word lines are formed in the core region. Thereby, the poly layer protects the substrate between the word lines from doping that could cause shorting between bit lines. According to another aspect of the invention, word lines are exposed while spacer material, dielectric, or like material protects the substrate between word lines. The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines even in virtual ground arrays where there are no oxide island isolation regions between bit lines.

Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

Abstract: An improved flash memory device, which has shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.

Abstract: A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric of the charge pump capacitor and the dielectric of the memory cell are formed during the same processing step.

Abstract: A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device.

Abstract: One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.

Abstract: A semiconductor chip having a plurality of flash memory devices, shallow trench isolation in the periphery region, and LOCOS isolation in the core region. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide barrier layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.