Abstract: A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.

Abstract: A method for making a ULSI MOSFET chip includes forming a MOSFET gate stack on a substrate, with a tunnel oxide layer being sandwiched between the gate stack and substrate. To prevent thickening of the tunnel oxide layer into a “gate edge lifting” profile during subsequent oxidation-causing steps, at least one protective barrier film is deposited or grown over the gate stack and tunnel oxide layer immediately after gate stack formation. Then, subsequent steps, including forming source and drain regions for the gate stack, can be undertaken without causing thickening of the tunnel oxide layer.

Abstract: A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.

Abstract: Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by reducing ARC loss during photoresist stripping associated with plural mask formation in the core memory cell region during patterning and ion implantations. Embodiments include sequentially etching the stacked gate electrode structure in the core memory cell region, photoresist stripping and etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, plural maskings and ion implantations are implemented in the core memory cell region with attendant photoresist strippings.

Abstract: A method and system for providing a semiconductor memory device is disclosed. The method and system include providing a plurality of gate stacks above a substrate. Each of the plurality of gate stacks includes a first edge and a second edge. The method and system also include providing a source implant adjacent to the first edge of each of the plurality of gate stacks and driving the source implant under the first edge of each of the plurality of gate stacks. The method and system also include providing a first spacer and a second spacer for each of the plurality of gate stacks. The first and second spacers are disposed along the first and second edges, respectively, of each of the plurality of gate stacks. The method and system also include providing a drain implant after source implant is driven under the first edge and after the first and second spacers are provided. The drain implant is in the substrate adjacent to the second spacer.

Abstract: The reliability of a tunnel oxide is improved by light doping of the floating gate, as with phosphorous or arsenic atoms. Doping can be implemented by ion implantation or by in situ deposition. The relatively low dopant concentration further enhances charge retention on the floating gate.

Abstract: A method for manufacturing a non-volatile memory device includes forming a memory device on the semiconductor substrate by forming isolation regions in said substrate, forming gate stacks on the substrate between respective ones of said isolation regions, with each stack having at least an active region adjacent thereto, and forming common source regions for the plurality of gate stacks through a plasma implant of an impurity. A memory device having a plurality of memory transistors is also provided. The device generally comprises a semiconductor substrate having a generally planar surface. Field oxide regions are formed in the semiconductor substrate to a depth below the substrate surface. The common bus region is provided which is exposed to the substrate, the common bus region including at least a first recessed portion of the substrate wherein areas of the field oxide regions have been removed so that said recessed portion has a depth below the surface of the substrate.

Abstract: Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during patterning and ion implantations. Embodiments include initially etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, processing in the core memory cell region is conducted by etching the stacked gate electrode structure and ion implanting to form the source/drains with attendant stripping of photoresist layers.

Abstract: Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during patterning and ion implantations. Processing is simplified by employing the same mask in the memory cell region for patterning the stacked gate electrode structure and for ion implanting the shallow source/drain extensions. Embodiments include initially etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, processing in the core memory cell region is conducted by etching the stacked gate electrode structure and ion implanting to form the source/drains with attendant stripping of photoresist layers.

Abstract: The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.

Abstract: The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH.sub.3 F)/oxygen (O.sub.2) etch chemistry is used to selectively remove the ARC layer. The CH.sub.3 F/O.sub.2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer or the tungsten contacts.

Abstract: The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by double-sided scrubbing the wafer prior to photolithography. It was found that particles adhering to the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Double-sided wafer scrubbing removes such adhering particles, thereby improving photolithographic accuracy.

Abstract: Outgassing from a dielectric gap fill layer, e.g., a low dielectric constant material such as HSQ, and attendant deformation or delamination of a barrier dielectric layer on an overlying patterned conductive layer during subsequent thermal processing are avoided or significantly reduced by controlling the thickness of the dielectric cap layer on the dielectric gap fill layer. Embodiments include depositing a conformal SiON barrier on a first conductive pattern, depositing a HSQ gap fill layer on the conformal SiON barrier layer, depositing a silicon oxide cap layer and planarizing such that the thickness of the planarized silicon cap layer is at least 2500 .ANG., thereby avoiding deformation and/or delamination of a conformal SiON barrier layer on an overlying patterned conductive layer during subsequent thermal processing.

Abstract: A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.

Abstract: Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer.

Abstract: Disclosed herein is a method of forming a silicon gate stack onto a silicon substrate for a silicon device. The method of forming the silicon gate stack comprises the steps of growing an oxide layer onto the silicon substrate, depositing a thin layer of silicon to form a thin layer of silicon over the oxide layer, depositing a thick layer of silicon over the thin layer of silicon, and introducing impurities into only the thick layer of silicon to form a silicon gate whereby the silicon gate includes the thin layer of silicon and the thick layer of silicon having the impurities. The impurities being introduced with a concentration, the impurities concentration and the thick layer thickness impeding an encroachment by the oxide layer into the silicon gate during application of a protective screen oxide layer around the silicon gate stack.

Abstract: A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.

Abstract: The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.

Abstract: After providing a patterned nitride layer over a patterned layer of oxide in turn disposed on a silicon substrate, a covering layer of oxide or polysilicon is deposited over the resulting structure to contact the substrate to hold the patterned nitride layer portions in position as field oxide is grown. In addition, field oxide growth rate slows at the edges of the nitride layer portions, allowing additional time for field oxide to flow as it is grown, relieving lifting force on the nitride layer portions, and providing an increase in silicon active area between field oxide regions.

Abstract: The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by polishing the wafer backside prior to photolithography. It was found that particles adhering to and/or scratches on the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Backside polishing, as by chemical-/mechanical polishing, removes such adhering particles and/or scratches, thereby improving photolithographic accuracy.