Patents by Inventor Mark Visokay

Mark Visokay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8962350
    Abstract: Multi-step deposition of lead-zirconium-titanate (PZT) ferroelectric material. An initial portion of the PZT material is deposited by metalorganic chemical vapor deposition (MOCVD) at a low deposition rate, for example at a temperature below about 640 deg C. from vaporized liquid precursors of lead, zirconium, and titanium, and a solvent at a collective flow rate below about 1.1 ml/min, in combination with an oxidizing gas. Following deposition of the PZT material at the low flow rate, the remainder of the PZT film is deposited at a high deposition rate, attained by changing one or more of precursor and solvent flow rate, oxygen concentration in the oxidizing gas, A/B ratio of the precursors, temperature, and the like.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: February 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Bhaskar Srinivasan, Brian E. Goodlin, Haowen Bu, Mark Visokay
  • Publication number: 20140225226
    Abstract: Multi-step deposition of lead-zirconium-titanate (PZT) ferroelectric material. An initial portion of the PZT material is deposited by metalorganic chemical vapor deposition (MOCVD) at a low deposition rate, for example at a temperature below about 640 deg C. from vaporized liquid precursors of lead, zirconium, and titanium, and a solvent at a collective flow rate below about 1.1 ml/min, in combination with an oxidizing gas. Following deposition of the PZT material at the low flow rate, the remainder of the PZT film is deposited at a high deposition rate, attained by changing one or more of precursor and solvent flow rate, oxygen concentration in the oxidizing gas, A/B ratio of the precursors, temperature, and the like.
    Type: Application
    Filed: January 30, 2014
    Publication date: August 14, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Bhaskar Srinivasan, Brian E. Goodlin, Haowen Bu, Mark Visokay
  • Patent number: 8183137
    Abstract: The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate (210). This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure (230), wherein the NMOS gate structure (230) includes an NMOS gate dielectric (240) and an NMOS gate electrode (250). This method further includes forming n-type source/drain regions (710) within the substrate (210) proximate the NMOS gate structure (230), and siliciding the NMOS gate electrode (250) to form a silicided gate electrode (1110, 1210). This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode (250) prior to or concurrently with siliciding.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: May 22, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Mark Visokay, Jorge Adrian Kittl
  • Patent number: 7812401
    Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm?3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: October 12, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Borna Obradovic, Shashank Ekbote, Mark Visokay
  • Publication number: 20100109089
    Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm?3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.
    Type: Application
    Filed: January 18, 2010
    Publication date: May 6, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Borna OBRADOVIC, Shashank EKBOTE, Mark VISOKAY
  • Patent number: 7682892
    Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm?3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: March 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Borna Obradovic, Shashank Ekbote, Mark Visokay
  • Patent number: 7531400
    Abstract: Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: May 12, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Mark Visokay, Luigi Colombo
  • Publication number: 20090057759
    Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm?3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.
    Type: Application
    Filed: August 31, 2007
    Publication date: March 5, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Borna Obradovic, Shashank Ekbote, Mark Visokay
  • Publication number: 20080290427
    Abstract: The invention provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming an NMOS gate structure over a substrate, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. The method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and forming a metal alloy layer over the NMOS gate electrode. The method additionally includes incorporating the metal alloy into the NMOS gate electrode to form an NMOS gate electrode fully silicided with the metal alloy.
    Type: Application
    Filed: May 23, 2007
    Publication date: November 27, 2008
    Applicant: Texas Instruments Inc.
    Inventors: Mark Visokay, Jorge Adrian Kittl
  • Publication number: 20080293193
    Abstract: Provided is a method for manufacturing a semiconductor device that includes forming a gate structure over a substrate, wherein the gate structure includes a gate dielectric and a gate electrode. The method further includes forming a metal layer over the gate electrode, and forming a fully silicided gate electrode using the metal layer. The fully silicided gate electrode may be formed by subjecting the gate electrode to a first anneal in a presence of the metal layer to form a silicided gate electrode, wherein a maximum temperature of the first anneal does not exceed about 340° C. The fully silicided gate electrode may further be formed by removing any unreacted portions of the metal layer after the first anneal, and subjecting the silicided gate electrode to a second anneal to form the fully silicided gate electrode subsequent to the removing. A maximum temperature of the second anneal exceeds about 400° C.
    Type: Application
    Filed: May 23, 2007
    Publication date: November 27, 2008
    Applicant: Texas Instruments Inc.
    Inventors: Mark Visokay, Jorge Adrian Kittl
  • Publication number: 20080290428
    Abstract: The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate. This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. This method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and siliciding the NMOS gate electrode to form a silicided gate electrode. This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode prior to or concurrently with siliciding.
    Type: Application
    Filed: May 23, 2007
    Publication date: November 27, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Mark Visokay, Jorge Adrian Kittl
  • Patent number: 7361599
    Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: April 22, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Theodore S. Moise, Guoqiang Xing, Mark Visokay, Justin F. Gaynor, Stephen R. Gilbert, Francis Celii, Scott R. Summerfelt, Luigi Colombo
  • Publication number: 20080057739
    Abstract: A method for improving high-? gate dielectric film (104) properties. The high-? film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
    Type: Application
    Filed: October 25, 2007
    Publication date: March 6, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Luigi Colombo, James Chambers, Mark Visokay, Antonio Rotondaro
  • Publication number: 20080044957
    Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
    Type: Application
    Filed: October 11, 2007
    Publication date: February 21, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: James Chambers, Mark Visokay, Luigi Colombo, Antonio Rotondaro
  • Publication number: 20070284676
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.
    Type: Application
    Filed: May 8, 2007
    Publication date: December 13, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Husam Alshareef, Mark Visokay, Antonio Rotondaro, Luigi Colombo
  • Publication number: 20070284608
    Abstract: A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.
    Type: Application
    Filed: August 27, 2007
    Publication date: December 13, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuanning Chen, Mark Visokay
  • Patent number: 7276408
    Abstract: A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: October 2, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Yuanning Chen, Mark Visokay
  • Patent number: 7253076
    Abstract: Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: August 7, 2007
    Assignee: Micron Technologies, Inc.
    Inventors: Vishnu K. Agarwal, Garo Derderian, Gurtej S. Sandhu, Weimin M. Li, Mark Visokay, Cem Basceri, Sam Yang
  • Patent number: 7253102
    Abstract: An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at least one of which is electrically conductive. The film may be formed in any convenient manner, such as by chemical vapor deposition techniques, which may be followed by an anneal to better define and/or crystallize the at least two phases. The film may be formed over an underlying conductive layer. At least one of the at least two phases is selectively removed from the film, such as by an etch process that preferentially etches at least one of the at least two phases so as to leave at least a portion of the electrically conductive phase. Ruthenium and ruthenium oxide, both conductive, may be used for the two or more phases. Iridium and its oxide, rhodium and its oxide, and platinum and platinum-rhodium may also be used. A wet etchant comprising ceric ammonium nitrate and acetic acid may be used.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: August 7, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Mark Visokay, Thomas M. Graettinger, Steven D. Cummings
  • Publication number: 20070122962
    Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
    Type: Application
    Filed: January 5, 2007
    Publication date: May 31, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Chambers, Mark Visokay, Luigi Colombo