Abstract: A three-state CMOS output buffer (200), having protective circuitry and an output node (OUT) connected to a bus, prevents damage to a connected integrated circuit when the bus voltage exceeds a power supply reference voltage (VCC). A final output stage of the output buffer (200) includes a first pull-up transistor (QP200), a clamping transistor (QN202), and a pull-down transistor (QN204). A half-pass circuit (QN200) blocks the output voltage from propagating through the final output stage to damage the output buffer (200) when the output voltage applied to the output node (OUT) exceeds the supply voltage. The protective circuitry uses a clamping circuit (210), a switching circuit (212) and a backgate bias circuit (206) to prevent a leakage path between the output node (OUT) and the power supply reference (VCC) through the source/bulk junction of biased transistors in the output buffer (200).

Abstract: A circuit (10) operates at relatively low values of the supply voltage, and includes a differential input circuit (16) which receives a differential input signal at first and second terminals (18, 21). A differential voltage derived by the input circuit from the differential input signal is present at third and fourth terminals (28, 31) and is amplified by a differential amplifier (12). A differential level adjuster (14) adjusts output voltages from the amplifier to suitable values for application to a matcher (15). The matcher (15) generates two currents that also flow within a differential compensator (17), and that match respective currents flowing in the amplifier. The differential compensator then provides a suitable current to each of the third and fourth terminals, such that the current flow between the first and third terminals, and between the second and fourth terminals, is substantially zero.