Abstract: A radio-frequency modulator apparatus comprises a baseband stage, a mixer stage and a radio-frequency stage. The baseband stage comprises: an input line for receiving an input current representative of a baseband input signal, a baseband transistor that passes some or all of the input current between a first and a second terminal thereof, an electrical connection between the input line and a control terminal of the baseband transistor, and an output line connected to said control terminal. The mixer stage receives a signal from the baseband stage and mixes it with a radio-frequency local-oscillator signal to generate a radio-frequency mixed signal. The radio-frequency stage receives the radio-frequency mixed signal, applies the radio-frequency mixed signal to a control terminal of a radio-frequency transistor causing it to pass a radio-frequency output current between a first and a second terminal thereof, and outputs the radio-frequency output current as an output signal.

Abstract: An RF amplifier comprises a first ‘transconductance’ transistor (NCS) arranged to receive an RF input voltage (RFIN) at its gate terminal. A second ‘cascode’ transistor (NCG) has its source terminal connected to the drain terminal of the first transistor (NCS) at a node (MID). A feedback circuit portion is configured to measure a node voltage at the node (MID), to determine an average of the node voltage, to compare said average node voltage to a predetermined reference voltage (VBCG), and to generate a control voltage (CGGATE) dependent on the difference between the average node voltage and the predetermined reference voltage (VBCG). The feedback circuit portion applies the control voltage (CGGATE) to the gate terminal of the second transistor (NCG).

Abstract: A power control system provides multiple supply voltages that are guaranteed not to violate boundary conditions regardless of the timing of voltage change commands. A first voltage (Vlogic in the embodiments described herein) is controlled conventionally, and a second voltage (Vmemory) is either selected or generated by adding a selected offset to the first voltage. Both the size of the offset, and the absolute value of the second voltage, are constrained at all times, by constraint values specific to the current voltage zone. The invention ensures a smooth transition between different voltage operating points, and ensures that the trajectory of change between specified operating points remains within predefined boundaries.

Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.

Abstract: A method for controlling powering of a mobile platform comprising a first Finite State Machine (FSM) and a second FSM. The method comprises synchronizing the first FSM with the second FSM, wherein the first FSM is arranged on a first Integrated Circuit (IC) comprised in the mobile platform and configured to control a first Power Management Unit (PMU) arranged on the first IC, and wherein the second FSM is arranged on a second IC comprised in the mobile platform and configured to control a second PMU arranged on the second IC, whereby the first PMU and the second PMU are synchronized to operate simultaneously during rank-up and rank-down, thereby providing power control of the mobile platform.

Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.

Abstract: A power control system provides multiple supply voltages that are guaranteed not to violate boundary conditions regardless of the timing of voltage change commands. A first voltage (Vlogic in the embodiments described herein) is controlled conventionally, and a second voltage (Vmemory) is either selected or generated by adding a selected offset to the first voltage. Both the size of the offset, and the absolute value of the second voltage, are constrained at all times, by constraint values specific to the current voltage zone. The invention ensures a smooth transition between different voltage operating points, and ensures that the trajectory of change between specified operating points remains within predefined boundaries.

Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.

Abstract: A power control system provides multiple supply voltages that are guaranteed not to violate boundary conditions regardless of the timing of voltage change commands. A first voltage (Vlogic in the embodiments described herein) is controlled conventionally, and a second voltage (Vmemory) is either selected, or generated by adding a selected offset to the first voltage. Both the size of the offset, and the absolute value of the second voltage, are constrained at all times, by constraint values specific to the current voltage zone. The invention ensures a smooth transition between different voltage operating points, and ensures that the trajectory of change between specified operating points remains within predefined boundaries.

Abstract: A method for controlling powering of a mobile platform comprising a first Finite State Machine (FSM) and a second FSM. The method comprises synchronizing the first FSM with the second FSM, wherein the first FSM is arranged on a first Integrated Circuit (IC) comprised in the mobile platform and configured to control a first Power Management Unit (PMU) arranged on the first IC, and wherein the second FSM is arranged on a second IC comprised in the mobile platform and configured to control a second PMU arranged on the second IC, whereby the first PMU and the second PMU are synchronized to operate simultaneously during rank-up and rank-down, thereby providing power control of the mobile platform.

Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.

Abstract: A method for controlling powering of a mobile platform 201 comprising a first Finite State Machine (FSM) 202 and a second FSM 203. The method comprises synchronizing the first FSM with the second FSM, wherein the first FSM is arranged on a first Integrated Circuit (IC) 207 comprised in the mobile platform and configured to control a first Power Management Unit (PMU) 205 arranged on the first IC, and wherein the second FSM is arranged on a second IC 208 comprised in the mobile platform and configured to control a second PMU 206 arranged on the second IC, whereby the first PMU and the second PMU are synchronized to operate simultaneously during rank-up and rank-down, thereby providing power control of the mobile platform.

Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable precharge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.

Abstract: A temperature sensor includes two branches, each branch having at least a first transistor and a second transistor connected as diodes and cascaded, so that an emitter of the first transistor is connected to a collector of the second transistor of the same branch. The temperature source also includes a current source configured to provide a current to the two branches, and an analog-to-digital convertor. The analog-to-digital convertor is connected to capture a voltage between emitters of the first transistors or of the second transistors, and is configured to convert said voltage to a digital temperature signal.

Abstract: A clock generation circuit generates clock signals of a requested frequency and relative phase by dividing a reference clock signal by counting reference clock signal pulses in a counter circuit. The clock generation circuit changes the frequency, and optionally also the phase, of an output clock signal upon request, without generating glitches or missing pulses. The clock generation circuit does not alter the frequency of the output clock signal until a phase pulse associated with the requested phase is asserted, and the counter circuit is in a predetermined state, such as a reset state.

Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable precharge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.

Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor. This limits the current through the first transistor and into the voltage setting circuit for the initial duration.

Abstract: A method for controlling powering of a mobile platform 201 comprising a first Finite State Machine (FSM) 202 and a second FSM 203. The method comprises synchronizing the first FSM with the second FSM, wherein the first FSM is arranged on a first Integrated Circuit (IC) 207 comprised in the mobile platform and configured to control a first Power Management Unit (PMU) 205 arranged on the first IC, and wherein the second FSM is arranged on a second IC 208 comprised in the mobile platform and configured to control a second PMU 206 arranged on the second IC, whereby the first PMU and the second PMU are synchronized to operate simultaneously during rank-up and rank-down, thereby providing power control of the mobile platform.

Abstract: A power control system provides multiple supply voltages that are guaranteed not to violate boundary conditions regardless of the timing of voltage change commands. A first voltage (Vlogic in the embodiments described herein) is controlled conventionally, and a second voltage (Vmemory) is either selected, or generated by adding a selected offset to the first voltage. Both the size of the offset, and the absolute value of the second voltage, are constrained at all times, by constraint values specific to the current voltage zone. The invention ensures a smooth transition between different voltage operating points, and ensures that the trajectory of change between specified operating points remains within predefined boundaries.

Abstract: A temperature sensor includes two branches, each branch having at least a first transistor and a second transistor connected as diodes and cascaded, so that an emitter of the first transistor is connected to a collector of the second transistor of the same branch. The temperature source also includes a current source configured to provide a current to the two branches, and an analog-to-digital convertor. The analog-to-digital convertor is connected to capture a voltage between emitters of the first transistors or of the second transistors, and is configured to convert said voltage to a digital temperature signal.