Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.

Abstract: A clock generation circuit generates clock signals of a requested frequency and relative phase by dividing a reference clock signal by counting reference clock signal pulses in a counter circuit. The clock generation circuit changes the frequency, and optionally also the phase, of an output clock signal upon request, without generating glitches or missing pulses. The clock generation circuit does not alter the frequency of the output clock signal until a phase pulse associated with the requested phase is asserted, and the counter circuit is in a predetermined state, such as a reset state.

Abstract: A clock generation circuit is operative to disable and enable a plurality of output clock signals while maintaining predetermined phase relationships between the clock signals. A reference clock signal is divided by a factor of at least two, to generate a master clock signal. A plurality of phase circuits, each independently enabled, generates a plurality of output clock signals by dividing the reference clock signal. The output clock signals have predetermined phase relationships relative to each other. Each phase circuit is enabled synchronously to a synchronization edge of the master clock signal. A synchronization circuit associated with each phase circuit ensures synchronization with the master clock signal by outputting a phase circuit enable signal only upon the conditions of a clock enable signal associated with the output clock being asserted and the receipt of a predetermined number of master clock signal synchronizing edges.

Abstract: In a wireless power charger a receiver (6) is inductively coupled to a transmitter (1) to receive power for charging an accumulator in a device (11). The receiver (6) communicates charging data to the transmitter (1) by imposing current pulses across the direct current output terminals of a rectifier (9) in the receiver. To enhance the performance of the receiver without reducing the signal to noise ratio of the current pulse receiver to transmitter communication the shape of unwanted transient currents in a filter capacitor (10) are sensed and the transient current shape added to an ideal rectangular step function pulse shape to produce a communication pulse shape. As a result the communication pulse shape seen at a secondary inductor (7) of the receiver closely approximates the ideal rectangular step function shape desired whereby the signal to noise ratio is kept high. The receiver is particularly useful in mobile devices such as cell phones, tablet PC's and laptops.

Abstract: There is provided a receiver comprising: a control unit for controlling the functions of the receiver; a receiving unit for receiving data signals and timing signals; and a digitally controlled delay line unit connected to the receiving unit and to the control unit. The control unit is configured to measure several samples of the received data signal and the timing signal, to determine average values of the several measured samples of the data signal and the timing signal for defining compensation values, and the digitally controlled delay line unit is configured to adjust the number of unit delay elements for compensating for skew between the data signal and the timing signal on the basis of the defined compensation values.

Abstract: There is provided a receiver comprising: a control unit for controlling the functions of the receiver; a receiving unit for receiving data signals and timing signals; and a digitally controlled delay line unit connected to the receiving unit and to the control unit. The control unit is configured to measure several samples of the received data signal and the timing signal, to determine average values of the several measured samples of the data signal and the timing signal for defining compensation values, and the digitally controlled delay line unit is configured to adjust the number of unit delay elements for compensating for skew between the data signal and the timing signal on the basis of the defined compensation values.