Abstract: Methods, systems, and devices for memory health status reporting are described. A memory device may output to a host device a parameter value, which may be indicative of metric or condition related to the performance or reliability (e.g., a health status) of the memory device of the memory device. The host device may thereby determine that the memory device is degraded, possibly prior to device or system failure. Based on the parameter value, the host device may take preventative action, such as quarantining the memory device, deactivating the memory device, or swapping the memory device for another memory device.

Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

Abstract: Methods, systems, and devices for memory health status reporting are described. A memory device may output to a host device a parameter value, which may be indicative of metric or condition related to the performance or reliability (e.g., a health status) of the memory device of the memory device. The host device may thereby determine that the memory device is degraded, possibly prior to device or system failure. Based on the parameter value, the host device may take preventative action, such as quarantining the memory device, deactivating the memory device, or swapping the memory device for another memory device.

Abstract: Methods, systems, and devices for interrupt signaling for a memory device are described. A memory device may transmit an interrupt signal to a host device to alter a sequence of operations that would otherwise be executed by the host device. The memory device may transmit the interrupt signal in response to detecting an error condition at the memory device, a performance degradation at the memory device, or another trigger event. In some examples, the memory device may include a dedicated interrupt pin for transmitting interrupt signals. Alternatively, the memory device may transmit interrupt signals via a pin also sued to transmit error detection codes. For example, the memory device may transmit an interrupt signal before or after an error detection code or may invert the error detection code to indicate the interrupt, in which case the inverted error detection code may act as an interrupt signal.

Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

Abstract: The invention relates to a method, to a first and a second device (1, 2) and to a system (10) comprising the first and second device (1, 2) for transferring data, said system and devices matching the user data transfer rate during the data transfer between the first and the second device (1, 2). The first device (1) comprises in particular a medium access controller and operates in the second layer according to the OSI reference model, whilst the second device (2) transmits and receives user data in the first layer according to the OSI reference model and comprises an interface unit (24) for a DSL connection. The transfer rate match is achieved in particular by PAUSE frames according to the IEEE 802.3-2004 standard and the second device also operates in the second layer according to the OSI reference model to transmit and receive the PAUSE frames.

Abstract: A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.

Abstract: A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.