Abstract: A method for transmitting data is disclosed, whereby data are transmitted in packets between a first device and a second device, whereby a further device disposed between the first device and the second device analyzes the packets at most for regeneration purposes. The second device transmits data between itself and a third device using DSL technology. During the data transmission between the first device and the second device a comparison of transmission rates takes place.

Abstract: A memory system, with a memory controller and a memory module, is configured to transfer error securing data and address signals within signal frames between the memory controller and the memory module. The memory system includes: an address register configured to pre-store an address signal associated with at least one block of data signals to be transferred, and at least one cyclic redundancy checksum calculator included in one of the memory controller and the memory module, the calculators being configured to calculate a cyclic redundancy checksum for the at least one data signal block, wherein the pre-stored address signal is used as an initial value for the calculation of the cyclic redundancy checksum and the at least one block of data and address signals are transferred together with the calculated cyclic redundancy checksum.

Abstract: A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.

Abstract: A method receives data including synchronization information. The method includes obtaining a synchronization for receiving the data based on the synchronization information. The method includes generating, during receiving of the data, maintenance information indicative of whether the synchronization is being maintained based on the synchronization information. The method includes continuing, upon loss of the synchronization, to generate the maintenance information based on the synchronization.

Abstract: A method of sending data on request from a memory to a device, wherein the memory receives a request from the device for sending predetermined data to the device, wherein the memory sends data and information about the data to the device.

Abstract: A method and apparatus for accessing a memory device. The method includes providing control signals for an access command to the memory device via an asynchronous interface and transmitting data for the access command to the memory device. The method also includes encoding, into the transmitted data, a clock signal. The encoded clock signal in the transmitted data is used by the memory device for receiving the data transmission.

Abstract: A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.

Abstract: A memory system, with a memory controller and a memory module, is configured to transfer error securing data and address signals within signal frames between the memory controller and the memory module. The memory system includes: an address register configured to pre-store an address signal associated with at least one block of data signals to be transferred, and at least one cyclic redundancy checksum calculator included in one of the memory controller and the memory module, the calculators being configured to calculate a cyclic redundancy checksum for the at least one data signal block, wherein the pre-stored address signal is used as an initial value for the calculation of the cyclic redundancy checksum and the at least one block of data and address signals are transferred together with the calculated cyclic redundancy checksum.

Abstract: A memory circuit comprises a D/A converter connected with an input/output circuit and with a writing circuit, wherein the D/A converter converts a digital data with at least two digital bits received from the input/output circuit to one analog value and forwards the analog value to the writing circuit, wherein the digital data is at least a part of a floating point number, wherein the writing circuit writes the analog value in at least one selected memory cell, and an A/D converter connected with a reading circuit and with the input/output circuit, wherein the reading circuit reads an analog value from a selected memory cell and forwards the analog value to the A/D converter, wherein the A/D converter converts the analog value to digital data, and wherein the A/D converter forwards the digital data to the input/output circuit.

Abstract: A memory element includes a memory which is operable according to operating parameters from at least two sets of operating parameter values and an operating parameter control which is implemented to receive operating state information and to select a set of operating parameter values for the operation of the memory based on the operating state information.

Abstract: A method for transmitting data is disclosed, whereby data are transmitted in packets between a first device and a second device, whereby a further device disposed between the first device and the second device analyzes the packets at most for regeneration purposes. The second device transmits data between itself and a third device using DSL technology. During the data transmission between the first device and the second device a comparison of transmission rates takes place.

Abstract: A method receives data including synchronization information. The method includes obtaining a synchronization for receiving the data based on the synchronization information. The method includes generating, during receiving of the data, maintenance information indicative of whether the synchronization is being maintained based on the synchronization information. The method includes continuing, upon loss of the synchronization, to generate the maintenance information based on the synchronization.

Abstract: Method of controlling a driver strength and a termination impedance of a signal line of an interface, wherein the driver sends an output signal as an alternating voltage with a frequency, wherein the signal line is terminated with a termination impedance, wherein the driver strength is changed depending on a changing of the frequency of the output signal.

Abstract: Methods and apparatus for storing data in different regions of the memory device based on, for example, a reliability requirement of the data. A memory controller may determine a category for data, for example, high reliability data and low reliability data, prior to storing the data in memory. The data may be stored in a region of memory associated with the category of data according to a method associated with the category of data. For example, high reliability data may be stored in a particular region of memory using lower clock frequencies, with additional error correction bits, and/or at multiple redundant locations. In contrast, low reliability data may be stored other regions of the memory using higher clock frequencies, without additional error correction bits and/or at singular locations (i.e., without redundant locations.

Abstract: A method and apparatus for accessing one or more memory devices using an optical multi-mode signal. The method includes providing an optical multi-mode signal including a first mode and a second mode and transmitting the optical multi-mode signal via an optical multi-mode bus to the one or more memory devices. The first mode is used to perform a first access to the one or more memory devices and the second mode is used to perform a second access to the one or more memory devices.

Abstract: A method and apparatus for accessing a memory device. The method includes providing control signals for an access command to the memory device via an asynchronous interface and transmitting data for the access command to the memory device. The method also includes encoding, into the transmitted data, a clock signal. The encoded clock signal in the transmitted data is used by the memory device for receiving the data transmission.

Abstract: A display having a screen, and memory for storing picture data is disclosed. In one embodiment, the screen includes a plurality of pixels, the pixels in a first mode of the display being controlled by the picture data stored in the memory, and in a second mode of the display being controlled by picture data received from an external processing unit.

Abstract: Method and apparatus for refreshing selective memory cells. A refresh circuit is connected with the memory cells and operates to refresh data stored in the memory cells on the basis of the values of valid bits having a predefined association with the memory cells.

Abstract: A method of sending data on request from a memory to a device, wherein the memory receives a request from the device for sending predetermined data to the device, wherein the memory sends data and information about the data to the device.

Abstract: A memory circuit comprises a D/A converter connected with an input/output circuit and with a writing circuit, wherein the D/A converter converts a digital data with at least two digital bits received from the input/output circuit to one analog value and forwards the analog value to the writing circuit, wherein the digital data is at least a part of a floating point number, wherein the writing circuit writes the analog value in at least one selected memory cell, and an A/D converter connected with a reading circuit and with the input/output circuit, wherein the reading circuit reads an analog value from a selected memory cell and forwards the analog value to the A/D converter, wherein the A/D converter converts the analog value to digital data, and wherein the A/D converter forwards the digital data to the input/output circuit.