Patents by Inventor Markus Bina
Markus Bina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11250966Abstract: An apparatus for processing a plurality of semiconductor wafers, the apparatus including a spallation chamber, a neutron producing material mounted in the spallation chamber, a neutron moderator, and an irradiation chamber coupled to the spallation chamber, wherein the neutron moderator is disposed between the spallation chamber and the irradiation chamber, wherein the irradiation chamber is configured to accommodate the plurality of semiconductor wafers, wherein each of the plurality of semiconductor wafers has a first surface and a second surface opposite the first surface, wherein the plurality of semiconductor wafers are positioned so that a first surface of one semiconductor wafer faces a second surface of another semiconductor wafer.Type: GrantFiled: September 13, 2019Date of Patent: February 15, 2022Assignee: Infineon Technologies AGInventors: Markus Bina, Hans-Joachim Schulze, Werner Schustereder
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Patent number: 11075290Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.Type: GrantFiled: May 10, 2019Date of Patent: July 27, 2021Assignees: Infineon Technologies AG, Infineon Technologies Dresden GmbH & Co. KGInventors: Matteo Dainese, Alexander Philippou, Markus Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
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Publication number: 20210226072Abstract: A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body; and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.Type: ApplicationFiled: March 17, 2021Publication date: July 22, 2021Inventors: Anton Mauder, Mario Barusic, Markus Bina, Matteo Dainese
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Patent number: 10978596Abstract: A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body: and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.Type: GrantFiled: August 17, 2018Date of Patent: April 13, 2021Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Mario Barusic, Markus Bina, Matteo Dainese
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Patent number: 10923578Abstract: A semiconductor device includes a transistor. The transistor includes a drift region of a first conductivity type in a semiconductor substrate having a first main surface, a body region of a second conductivity type between the drift region and the first main surface, and a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas including a first mesa and a dummy mesa. The plurality of trenches includes at least one active trench. The first mesa is arranged at a first side of the active trench, and the dummy mesa is arranged at a second side of the active trench. A gate electrode is arranged in the active trench, and a source region of the first conductivity type is in the first mesa. A one-sided channel of the transistor is configured to be formed in the first mesa.Type: GrantFiled: December 13, 2018Date of Patent: February 16, 2021Assignee: Infineon Technologies Austria AGInventors: Caspar Leendertz, Markus Bina, Matteo Dainese, Alice Pei-Shan Hsieh, Christian Philipp Sandow
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Patent number: 10903353Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.Type: GrantFiled: March 5, 2019Date of Patent: January 26, 2021Assignee: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Markus Bina, Anton Mauder, Jens Barrenscheen
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Patent number: 10840362Abstract: A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region.Type: GrantFiled: October 23, 2018Date of Patent: November 17, 2020Assignee: Infineon Technologies AGInventors: Alexander Philippou, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow
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Patent number: 10644141Abstract: A power semiconductor device having an IGBT-configuration includes at least one power cell. Each power cell includes at least three trenches arranged laterally adjacent to each other. Each trench extends into a semiconductor body along a vertical direction and includes an insulator that insulates a respective electrode from the semiconductor body. The at least three trenches include at least one control trench whose electrode is electrically coupled to a control terminal, and a source trench whose electrode is electrically coupled to a first load terminal. An active mesa for conduction of at least a part of the load current is laterally confined at least by one of the at least one control trench and includes at least a respective section of each of a source region and a channel region. An auxiliary mesa is laterally confined by the source trench and one of the at least one control trench.Type: GrantFiled: January 7, 2019Date of Patent: May 5, 2020Assignee: Infineon Technologies Austria AGInventors: Caspar Leendertz, Markus Bina, Christian Philipp Sandow
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Publication number: 20200136608Abstract: In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.Type: ApplicationFiled: December 20, 2019Publication date: April 30, 2020Inventors: Markus Bina, Jens Barrenscheen, Anton Mauder
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Patent number: 10615272Abstract: A method of processing a semiconductor device includes: providing a semiconductor body with a drift region; forming trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement having a lateral structure so that some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; subjecting the semiconductor body and the mask arrangement to a dopant material providing step to form a plurality of doping regions of a second conductivity type below bottoms of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step so that the doping regions extend in parallel to the first lateral direction and overlap to form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.Type: GrantFiled: October 23, 2018Date of Patent: April 7, 2020Assignee: Infineon Technologies AGInventors: Antonio Vellei, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
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Patent number: 10546939Abstract: A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body. The semiconductor body further comprises: a barrier region and a drift volume having at least a first drift region wherein the barrier region couples the first drift region with the semiconductor channel region.Type: GrantFiled: May 24, 2019Date of Patent: January 28, 2020Assignee: Infineon Technologies AGInventors: Roman Baburske, Markus Bina, Hans-Joachim Schulze, Oana Julia Spulber
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Patent number: 10530360Abstract: In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.Type: GrantFiled: February 22, 2017Date of Patent: January 7, 2020Assignee: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Markus Bina, Anton Mauder, Jens Barrenscheen
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Publication number: 20200005957Abstract: An apparatus for processing a plurality of semiconductor wafers, the apparatus including a spallation chamber, a neutron producing material mounted in the spallation chamber, a neutron moderator, and an irradiation chamber coupled to the spallation chamber, wherein the neutron moderator is disposed between the spallation chamber and the irradiation chamber, wherein the irradiation chamber is configured to accommodate the plurality of semiconductor wafers, wherein each of the plurality of semiconductor wafers has a first surface and a second surface opposite the first surface, wherein the plurality of semiconductor wafers are positioned so that a first surface of one semiconductor wafer faces a second surface of another semiconductor wafer.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Markus BINA, Hans-Joachim Schulze, Werner Schustereder
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Patent number: 10468148Abstract: In various embodiments, a method of processing one or more semiconductor wafers is provided. The method includes positioning the one or more semiconductor wafers in an irradiation chamber, generating a neutron flux in a spallation chamber coupled to the irradiation chamber, moderating the neutron flux to produce a thermal neutron flux, and exposing the one or more semiconductor wafers to the thermal neutron flux to thereby induce the creation of dopant atoms in the one or more semiconductor wafers.Type: GrantFiled: April 24, 2017Date of Patent: November 5, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Markus Bina, Hans-Joachim Schulze, Werner Schustereder
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Publication number: 20190288088Abstract: A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body. The semiconductor body further comprises: a barrier region and a drift volume having at least a first drift region wherein the barrier region couples the first drift region with the semiconductor channel region.Type: ApplicationFiled: May 24, 2019Publication date: September 19, 2019Applicant: Infineon Technologies AGInventors: Roman Baburske, Markus Bina, Hans-Joachim Schulze, Oana Julia Spulber
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Publication number: 20190273155Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.Type: ApplicationFiled: May 10, 2019Publication date: September 5, 2019Inventors: Matteo Dainese, Alexander Philippou, Markus Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
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Publication number: 20190259863Abstract: A chip includes a semiconductor body coupled to a first and a second load terminal. The semiconductor body includes an active region including a plurality of breakthrough cells, each of the breakthrough cells includes: an insulation structure; a drift region; an anode region, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal; a first barrier region arranged in contact with each of the anode region and the insulation structure, where the first barrier region of the plurality of breakthrough cells forms a contiguous semiconductor layer; a second barrier region separating each of the anode region and at least a part of the first barrier region from the drift region; and a doped contact region arranged in contact with the second load terminal, where the drift region is positioned between the second barrier region and the doped contact region.Type: ApplicationFiled: May 3, 2019Publication date: August 22, 2019Applicant: Infineon Technologies Austria AGInventors: Markus BINA, Thomas BASLER, Matteo DAINESE, Hans-Joachim SCHULZE
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Patent number: 10355116Abstract: A power semiconductor device includes: a semiconductor body coupled to a first load terminal and a second load terminal, and includes: a first doped region of a second conductivity type electrically connected to the first load terminal; a recombination zone arranged at least within the first doped region; an emitter region of the second conductivity type electrically connected to the second load terminal; and a drift region of a first conductivity type arranged between the first doped region and the emitter region. The drift region and the first doped region enable the power semiconductor device to operate in: a conducting state during which a load current between the load terminals is conducted along a forward direction; in a forward blocking state during which a forward voltage applied between the load terminals is blocked; and in a reverse blocking state during which a reverse voltage applied between the terminals is blocked.Type: GrantFiled: March 20, 2018Date of Patent: July 16, 2019Assignee: Infineon Technologies Austria AGInventors: Markus Bina, Thomas Basler, Matteo Dainese, Hans-Joachim Schulze
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Publication number: 20190214490Abstract: A power semiconductor device having an IGBT-configuration includes at least one power cell. Each power cell includes at least three trenches arranged laterally adjacent to each other. Each trench extends into a semiconductor body along a vertical direction and includes an insulator that insulates a respective electrode from the semiconductor body. The at least three trenches include at least one control trench whose electrode is electrically coupled to a control terminal, and a source trench whose electrode is electrically coupled to a first load terminal. An active mesa for conduction of at least a part of the load current is laterally confined at least by one of the at least one control trench and includes at least a respective section of each of a source region and a channel region. An auxiliary mesa is laterally confined by the source trench and one of the at least one control trench.Type: ApplicationFiled: January 7, 2019Publication date: July 11, 2019Inventors: Caspar Leendertz, Markus Bina, Christian Philipp Sandow
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Publication number: 20190198664Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.Type: ApplicationFiled: March 5, 2019Publication date: June 27, 2019Inventors: Markus Bina, Anton Mauder, Jens Barrenscheen