Patents by Inventor Markus Bina
Markus Bina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10332973Abstract: A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body. The semiconductor body further comprises: a barrier region and a drift volume having at least a first drift region wherein the barrier region couples the first drift region with the semiconductor channel region.Type: GrantFiled: May 22, 2018Date of Patent: June 25, 2019Assignee: Infineon Technologies AGInventors: Roman Baburske, Markus Bina, Hans-Joachim Schulze, Oana Julia Spulber
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Publication number: 20190189772Abstract: A semiconductor device includes a transistor. The transistor includes a drift region of a first conductivity type in a semiconductor substrate having a first main surface, a body region of a second conductivity type between the drift region and the first main surface, and a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas including a first mesa and a dummy mesa. The plurality of trenches includes at least one active trench. The first mesa is arranged at a first side of the active trench, and the dummy mesa is arranged at a second side of the active trench. A gate electrode is arranged in the active trench, and a source region of the first conductivity type is in the first mesa. A one-sided channel of the transistor is configured to be formed in the first mesa.Type: ApplicationFiled: December 13, 2018Publication date: June 20, 2019Inventors: Caspar Leendertz, Markus Bina, Matteo Dainese, Alice Pei-Shan Hsieh, Christian Philipp Sandow
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Patent number: 10304952Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.Type: GrantFiled: May 25, 2018Date of Patent: May 28, 2019Assignee: Infineon Technologies AGInventors: Matteo Dainese, Alexander Philippou, Markus Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
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Patent number: 10276681Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.Type: GrantFiled: February 29, 2016Date of Patent: April 30, 2019Assignee: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Markus Bina, Anton Mauder, Jens Barrenscheen
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Publication number: 20190123186Abstract: A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region.Type: ApplicationFiled: October 23, 2018Publication date: April 25, 2019Inventors: Alexander Philippou, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Francisco Javier Santos Rodriguez, Antonio Vellei, Caspar Leendertz, Christian Philipp Sandow
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Publication number: 20190123185Abstract: A method of processing a semiconductor device includes: providing a semiconductor body with a drift region; forming trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement having a lateral structure so that some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; subjecting the semiconductor body and the mask arrangement to a dopant material providing step to form a plurality of doping regions of a second conductivity type below bottoms of the exposed trenches; removing the mask arrangement; subjecting the semiconductor body to a temperature annealing step so that the doping regions extend in parallel to the first lateral direction and overlap to form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.Type: ApplicationFiled: October 23, 2018Publication date: April 25, 2019Inventors: Antonio Vellei, Markus Bina, Matteo Dainese, Christian Jaeger, Johannes Georg Laven, Alexander Philippou, Francisco Javier Santos Rodriguez
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Publication number: 20190058065Abstract: A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body: and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.Type: ApplicationFiled: August 17, 2018Publication date: February 21, 2019Inventors: Anton Mauder, Mario Barusic, Markus Bina, Matteo Dainese
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Patent number: 10153764Abstract: A semiconductor device includes a first load terminal, a second load terminal and a semiconductor body coupled to the first load terminal and the second load terminal. The semiconductor body is configured to conduct a load current along a load current path between the first load terminal and the second load terminal. The semiconductor device further includes a control electrode electrically insulated from the semiconductor body and configured to control a part of the load current path, and an electrically floating sensor electrode arranged adjacent to the control electrode. The sensor electrode is electrically insulated from each of the semiconductor body, and the control electrode and is capacitively coupled to the load current path.Type: GrantFiled: December 13, 2016Date of Patent: December 11, 2018Assignee: Infineon Technologies AGInventors: Markus Bina, Jens Barrenscheen, Anton Mauder
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Publication number: 20180342605Abstract: A power semiconductor device includes an active region surrounded by an inactive termination region each formed by part of a semiconductor body. The active region conducts load current between first and second load terminals. At least one power cell has trenches extending into the semiconductor body adjacent to each other along a first lateral direction and having a stripe configuration that extends along a second lateral direction into the active region. The trenches spatially confine a plurality of mesas each having at least one first type mesa electrically connected to the first load terminal and configured to conduct at least a part of the load current, and at least one second type mesa configured to not conduct the load current. A decoupling structure separates at least one of the second type mesas into a first section in the active region and a second section in the termination region.Type: ApplicationFiled: May 25, 2018Publication date: November 29, 2018Inventors: Matteo Dainese, Alexander Philippou, Markus Bina, Ingo Dirnstorfer, Erich Griebl, Christian Jaeger, Johannes Georg Laven, Caspar Leendertz, Frank Dieter Pfirsch
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Publication number: 20180308698Abstract: In various embodiments, a method of processing one or more semiconductor wafers is provided. The method includes positioning the one or more semiconductor wafers in an irradiation chamber, generating a neutron flux in a spallation chamber coupled to the irradiation chamber, moderating the neutron flux to produce a thermal neutron flux, and exposing the one or more semiconductor wafers to the thermal neutron flux to thereby induce the creation of dopant atoms in the one or more semiconductor wafers.Type: ApplicationFiled: April 24, 2017Publication date: October 25, 2018Inventors: Markus Bina, Hans-Joachim Schulze, Werner Schustereder
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Patent number: 10109624Abstract: An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.Type: GrantFiled: April 20, 2017Date of Patent: October 23, 2018Assignee: Infineon Technologies AGInventors: Markus Bina, Franz-Josef Niedernostheide, Alexander Philippou
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Publication number: 20180269304Abstract: A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body. The semiconductor body further comprises: a barrier region and a drift volume having at least a first drift region wherein the barrier region couples the first drift region with the semiconductor channel region.Type: ApplicationFiled: May 22, 2018Publication date: September 20, 2018Applicant: Infineon Technologies AGInventors: Roman Baburske, Markus Bina, Hans-Joachim Schulze, Oana Julia Spulber
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Publication number: 20180269313Abstract: A power semiconductor device includes: a semiconductor body coupled to a first load terminal and a second load terminal, and includes: a first doped region of a second conductivity type electrically connected to the first load terminal; a recombination zone arranged at least within the first doped region; an emitter region of the second conductivity type electrically connected to the second load terminal; and a drift region of a first conductivity type arranged between the first doped region and the emitter region. The drift region and the first doped region enable the power semiconductor device to operate in: a conducting state during which a load current between the load terminals is conducted along a forward direction; in a forward blocking state during which a forward voltage applied between the load terminals is blocked; and in a reverse blocking state during which a reverse voltage applied between the terminals is blocked.Type: ApplicationFiled: March 20, 2018Publication date: September 20, 2018Applicant: Infineon Technologies Austria AGInventors: Markus Bina, Thomas Basler, Matteo DAINESE, Hans-Joachim SCHULZE
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Patent number: 9978851Abstract: A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body. The semiconductor body further comprises: a barrier region and a drift volume having at least a first drift region wherein the barrier region couples the first drift region with the semiconductor channel region.Type: GrantFiled: July 12, 2017Date of Patent: May 22, 2018Assignee: Infineon Technologies AGInventors: Roman Baburske, Markus Bina, Hans-Joachim Schulze, Oana Julia Spulber
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Publication number: 20180019319Abstract: A power semiconductor device having a semiconductor body configured to conduct a load current is disclosed. In one example, the device includes a source region having dopants of a first conductivity type; a semiconductor channel region implemented in the semiconductor body and separating the source region from a remaining portion of the semiconductor body; a trench of a first trench type extending in the semiconductor body along an extension direction and being arranged adjacent to the semiconductor channel region, the trench of the first trench type including a control electrode that is insulated from the semiconductor body. The semiconductor body further comprises: a barrier region and a drift volume having at least a first drift region wherein the barrier region couples the first drift region with the semiconductor channel region.Type: ApplicationFiled: July 12, 2017Publication date: January 18, 2018Applicant: Infineon Technologies AGInventors: Roman Baburske, Markus Bina, Hans-Joachim Schulze, Oana Julia Spulber
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Publication number: 20170309619Abstract: An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.Type: ApplicationFiled: April 20, 2017Publication date: October 26, 2017Applicant: Infineon Technologies AGInventors: Markus Bina, Franz-Josef Niedernostheide, Alexander Philippou
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Publication number: 20170250260Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.Type: ApplicationFiled: February 29, 2016Publication date: August 31, 2017Inventors: Markus Bina, Anton Mauder, Jens Barrenscheen
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Publication number: 20170250685Abstract: In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.Type: ApplicationFiled: February 22, 2017Publication date: August 31, 2017Inventors: Markus Bina, Anton Mauder, Jens Barrenscheen
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Publication number: 20170170823Abstract: A semiconductor device includes a first load terminal, a second load terminal and a semiconductor body coupled to the first load terminal and the second load terminal. The semiconductor body is configured to conduct a load current along a load current path between the first load terminal and the second load terminal. The semiconductor device further includes a control electrode electrically insulated from the semiconductor body and configured to control a part of the load current path, and an electrically floating sensor electrode arranged adjacent to the control electrode. The sensor electrode is electrically insulated from each of the semiconductor body, and the control electrode and is capacitively coupled to the load current path.Type: ApplicationFiled: December 13, 2016Publication date: June 15, 2017Inventors: Markus Bina, Jens Barrenscheen, Anton Mauder