Patents by Inventor Markus Brink

Markus Brink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220005999
    Abstract: Techniques facilitating formation of amorphous superconducting alloys for superconducting circuits are provided. A device can comprise one or more superconducting components that comprise an amorphous superconducting alloy comprising two or more elements. At least one element of the two or more elements is a superconducting element.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 6, 2022
    Inventors: Christian Lavoie, Benjamin Wymore, Markus Brink, Stephen L. Brown
  • Publication number: 20210397774
    Abstract: Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 23, 2021
    Applicant: International Business Machines Corporation
    Inventors: Dongbing SHAO, Markus Brink
  • Publication number: 20210399199
    Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 23, 2021
    Inventors: Vivekananda P. Adiga, Martin O. Sandberg, Jeng-Bang Yau, Keith Fogel, John Bruley, Markus Brink, Benjamin Wymore
  • Patent number: 11205035
    Abstract: Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: December 21, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dongbing Shao, Markus Brink
  • Patent number: 11195982
    Abstract: In an embodiment, a method includes forming a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonance frequency. In an embodiment, the method includes forming a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits, the at least one conductive surface having at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dongbing Shao, Markus Brink, Firat Solgun, Jared Barney Hertzberg
  • Patent number: 11195799
    Abstract: Systems and techniques that facilitate hybrid readout packaging for quantum multichip bonding are provided. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, a readout resonator (e.g., input/output port) of one or more qubits on the first quantum chip can be routed to an inner portion of the interposer. In various instances, the inner portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonator to the inner portion can reduce a number of crossings and/or intersections between input/output lines on the interposer and connection buses between qubits on the interposer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dongbing Shao, Eric Peter Lewandowski, Nicholas Torleiv Bronn, Markus Brink
  • Publication number: 20210305315
    Abstract: A system includes a first quantum circuit plane that includes a first qubit, a second qubit and a third qubit. A coupled-line bus is coupled between the first qubit and the second qubit. A second circuit plane is connected to the first quantum circuit plane, comprising a control line coupled to the third qubit. The control line and the coupled-line bus are on different planes and crossing over each other, and configured to mitigate cross-talk caused by the crossing during signal transmission.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Inventors: Firat Solgun, Dongbing Shao, Markus Brink
  • Publication number: 20210305165
    Abstract: Systems and techniques that facilitate hybrid readout packaging for quantum multichip bonding are provided. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, a readout resonator (e.g., input/output port) of one or more qubits on the first quantum chip can be routed to an inner portion of the interposer. In various instances, the inner portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonator to the inner portion can reduce a number of crossings and/or intersections between input/output lines on the interposer and connection buses between qubits on the interposer.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Inventors: Dongbing Shao, Eric Peter Lewandowski, Nicholas Torleiv Bronn, Markus Brink
  • Patent number: 11088310
    Abstract: On a first superconducting layer deposited on a first surface of a substrate, a first component of a resonator is pattered. On a second superconducting layer deposited on a second surface of the substrate, a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via (TSV).
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua M. Rubin, Jared Barney Hertzberg, Sami Rosenblatt, Vivekananda P. Adiga, Markus Brink, Arvind Kumar
  • Patent number: 11088311
    Abstract: Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 10, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sami Rosenblatt, Rasit Onur Topaloglu, Markus Brink
  • Patent number: 11069849
    Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sami Rosenblatt
  • Publication number: 20210217948
    Abstract: Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.
    Type: Application
    Filed: November 4, 2019
    Publication date: July 15, 2021
    Inventors: Sami Rosenblatt, Rasit Onur Topaloglu, Markus Brink
  • Publication number: 20210183793
    Abstract: According to an embodiment of the present invention, a quantum processor includes a qubit chip. The qubit chip includes a substrate, and a plurality of qubits formed on a first surface of the substrate. The plurality of qubits are arranged in a pattern, wherein nearest-neighbor qubits in the pattern are connected. The quantum processor also includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, wherein the first and second qubits are separated by at least a third qubit in the pattern.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 17, 2021
    Inventors: Dongbing Shao, Markus Brink, Martin O. Sandberg, Vivekananda P. Adiga
  • Patent number: 11038093
    Abstract: A configuration of wirebonds for reducing cross-talk in a quantum computing chip includes a first wirebond coupling a first conductor of a quantum computing circuit with a first conductor of an external circuit. The embodiment further includes in the configuration a second wirebond coupling a second conductor of the quantum computing circuit with a second conductor of the external circuit, wherein the first wirebond and the second wirebond are separated by a first vertical distance in a direction of a length of the first conductor.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 15, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dongbing Shao, Markus Brink
  • Publication number: 20210151656
    Abstract: A configuration of wirebonds for reducing cross-talk in a quantum computing chip includes a first wirebond coupling a first conductor of a quantum computing circuit with a first conductor of an external circuit. The embodiment further includes in the configuration a second wirebond coupling a second conductor of the quantum computing circuit with a second conductor of the external circuit, wherein the first wirebond and the second wirebond are separated by a first vertical distance in a direction of a length of the first conductor.
    Type: Application
    Filed: July 30, 2020
    Publication date: May 20, 2021
    Applicant: International Business Machines Corporation
    Inventors: Dongbing Shao, Markus Brink
  • Patent number: 11005022
    Abstract: Techniques for a vertical Josephson junction superconducting device using microstrip waveguides are provided. In one embodiment, a chip surface base device structure is provided that comprises a superconducting material located on a first side of a substrate, and a second superconducting material located on a second side of the substrate and stacked on a second substrate, wherein the first side of the substrate and the second side of the substrate are opposite sides. In one implementation, the substrate or the second substrate, or the substrate and the second substrate are crystalline silicon. In one implementation, the chip surface base device structure also comprises a transmon qubit comprising a capacitor and a Josephson junction formed in a via of the substrate and comprising a tunnel barrier. In one implementation, the chip surface base device structure also comprises a microstrip line electrically coupled to the transmon qubit.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sami Rosenblatt, Rasit Onur Topaloglu
  • Patent number: 10976671
    Abstract: A technique relates to correcting an area of overlap between two films created by sequential shadow mask evaporations. At least one process is performed of: correcting design features in an original layout to generate a corrected layout using a software tool, such that the corrected layout modifies shapes of the design features and correcting the design features in the original layout to generate the corrected layout using a lithographic tool, such that the corrected layout modifies the shapes of the design features. The modified shapes of the design features are patterned at locations on a wafer according to the corrected layout using the lithographic tool. A first film is deposited by an initial shadow mask evaporation and a second film by a subsequent shadow mask evaporation to produce corrected junctions at the locations on the wafer, such that the first film and the second film have an overlap.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Brink, Sami Rosenblatt, Bryan D. Trimm
  • Publication number: 20210091295
    Abstract: A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 25, 2021
    Applicant: International Business Machines Corporation
    Inventors: DONGBING SHAO, Markus Brink, Firat Solgun, Jared Barney Hertzberg
  • Publication number: 20210057484
    Abstract: Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material.
    Type: Application
    Filed: September 15, 2020
    Publication date: February 25, 2021
    Inventors: Sami Rosenblatt, Jared Barney Hertzberg, Rasit Onur Topaloglu, Markus Brink
  • Publication number: 20210057630
    Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 25, 2021
    Inventors: Markus Brink, Jared B. Hertzberg, Sami Rosenblatt