Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.

Abstract: Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

Abstract: In an embodiment, a method includes forming a first chip having a first substrate and one or more qubits disposed on the first substrate, each of the one or more qubits having an associated resonance frequency. In an embodiment, the method includes forming a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits, the at least one conductive surface having at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

Abstract: Systems and techniques that facilitate hybrid readout packaging for quantum multichip bonding are provided. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, a readout resonator (e.g., input/output port) of one or more qubits on the first quantum chip can be routed to an inner portion of the interposer. In various instances, the inner portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonator to the inner portion can reduce a number of crossings and/or intersections between input/output lines on the interposer and connection buses between qubits on the interposer.

Abstract: Systems and techniques that facilitate hybrid readout packaging for quantum multichip bonding are provided. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, a readout resonator (e.g., input/output port) of one or more qubits on the first quantum chip can be routed to an inner portion of the interposer. In various instances, the inner portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonator to the inner portion can reduce a number of crossings and/or intersections between input/output lines on the interposer and connection buses between qubits on the interposer.

Abstract: A system includes a first quantum circuit plane that includes a first qubit, a second qubit and a third qubit. A coupled-line bus is coupled between the first qubit and the second qubit. A second circuit plane is connected to the first quantum circuit plane, comprising a control line coupled to the third qubit. The control line and the coupled-line bus are on different planes and crossing over each other, and configured to mitigate cross-talk caused by the crossing during signal transmission.

Abstract: On a first superconducting layer deposited on a first surface of a substrate, a first component of a resonator is pattered. On a second superconducting layer deposited on a second surface of the substrate, a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via (TSV).

Abstract: Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.

Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.

Abstract: Techniques related to a three-dimensional integration for qubits on multiple height crystalline dielectric and method of fabricating the same are provided. A superconductor structure can comprise a first buried layer that can comprise a first patterned superconducting layer of a first wafer bonded to a second patterned superconducting layer of a second wafer. The superconductor structure can also comprise a patterned superconducting film attached to the second wafer. Further, the superconductor structure can comprise a second buried layer that can comprise a third patterned superconducting layer of a third wafer bonded to the patterned superconducting film that can be attached to the second wafer.

Abstract: According to an embodiment of the present invention, a quantum processor includes a qubit chip. The qubit chip includes a substrate, and a plurality of qubits formed on a first surface of the substrate. The plurality of qubits are arranged in a pattern, wherein nearest-neighbor qubits in the pattern are connected. The quantum processor also includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, wherein the first and second qubits are separated by at least a third qubit in the pattern.

Abstract: A configuration of wirebonds for reducing cross-talk in a quantum computing chip includes a first wirebond coupling a first conductor of a quantum computing circuit with a first conductor of an external circuit. The embodiment further includes in the configuration a second wirebond coupling a second conductor of the quantum computing circuit with a second conductor of the external circuit, wherein the first wirebond and the second wirebond are separated by a first vertical distance in a direction of a length of the first conductor.

Abstract: A configuration of wirebonds for reducing cross-talk in a quantum computing chip includes a first wirebond coupling a first conductor of a quantum computing circuit with a first conductor of an external circuit. The embodiment further includes in the configuration a second wirebond coupling a second conductor of the quantum computing circuit with a second conductor of the external circuit, wherein the first wirebond and the second wirebond are separated by a first vertical distance in a direction of a length of the first conductor.

Abstract: Techniques for a vertical Josephson junction superconducting device using microstrip waveguides are provided. In one embodiment, a chip surface base device structure is provided that comprises a superconducting material located on a first side of a substrate, and a second superconducting material located on a second side of the substrate and stacked on a second substrate, wherein the first side of the substrate and the second side of the substrate are opposite sides. In one implementation, the substrate or the second substrate, or the substrate and the second substrate are crystalline silicon. In one implementation, the chip surface base device structure also comprises a transmon qubit comprising a capacitor and a Josephson junction formed in a via of the substrate and comprising a tunnel barrier. In one implementation, the chip surface base device structure also comprises a microstrip line electrically coupled to the transmon qubit.

Abstract: A technique relates to correcting an area of overlap between two films created by sequential shadow mask evaporations. At least one process is performed of: correcting design features in an original layout to generate a corrected layout using a software tool, such that the corrected layout modifies shapes of the design features and correcting the design features in the original layout to generate the corrected layout using a lithographic tool, such that the corrected layout modifies the shapes of the design features. The modified shapes of the design features are patterned at locations on a wafer according to the corrected layout using the lithographic tool. A first film is deposited by an initial shadow mask evaporation and a second film by a subsequent shadow mask evaporation to produce corrected junctions at the locations on the wafer, such that the first film and the second film have an overlap.

Abstract: A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.

Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.

Abstract: Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material.

Abstract: The present invention provides a process and structure of microfabricated air bridges for planar microwave resonator circuits. In an embodiment, the invention includes depositing a superconducting film on a surface of a base material, where the superconducting film is formed with a compressive stress, where the compressive stress is higher than a critical buckling stress of a defined structure, etching an exposed area of the superconducting film, thereby creating the at least one bridge, etching the base material, thereby forming a gap between the at least one bridge and the base material, depositing the at least one metal line on at least part of the superconducting film and at least part of the base material, where the at least one metal line runs under the bridge.

Abstract: A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.